Silicon Carbide (SiC) and Gallium Nitride (GaN) are revolutionizing power electronics with greater efficiency and durability than Silicon. Nevertheless, their widespread use is limited by reliability challenges, including thermal degradation, defect propagation, and charge trapping, affecting their stability and lifetime. This review explores these reliability issues, comparing empirical and physics-based models for predicting device performance and identifying practical limitations. We also examine strategies to enhance robustness, from material design improvements to advanced testing methods. We propose a demonstrative GaN power circuit topology specifically for demonstrating reliability in real-world conditions. This work highlights key challenges and opportunities in developing more reliable SiC and GaN technologies for future applications.

This work investigates bias-temperature instability (BTI) in 1700 V 4H-SiC MOSFETs under realistic 1 MHz switching conditions with simultaneous gate and drain stress. Threshold-voltage measurements reveal that the degradation does not follow the classical Reaction–Diffusion behavior typically assumed for silicon devices. Instead, the power-law exponent n shows a clear increase at the largest negative gate bias (−10 V), indicating a field-driven trap-generation mechanism. Temperature-dependent stress tests further show a negative activation energy (−0.466 eV), consistent with degradation accelerating at lower temperatures due to suppressed detrapping. The results demonstrate that conventional silicon BTI models cannot be directly applied to SiC technologies and that fixed-n lifetime extrapolation leads to significant errors. A bias-dependent, field-driven framework for estimating time-to-failure is proposed, offering more accurate and practical reliability prediction for high-power SiC converter applications.

This work examines resistance drift in FPGA I/O paths subjected to combined electrical and thermal stress, using a Xilinx Spartan-6 device as a representative platform. A multiplexed measurement approach was employed, in which multiple I/O pins were externally shorted and sequentially activated, enabling precise tracking of voltage, current, and effective series resistance over time, under controlled bias conditions. Two accelerated stress modes were investigated: high-temperature dwell in the range of 80–120 °C and thermal cycling between 80 and 140 °C. Both stress modes exhibited similar sub-linear (power-law) time dependence on resistance change, indicating cumulative degradation behavior. However, Arrhenius analysis revealed a strong contrast in effective activation energy: approximately 0.62 eV for high-temperature dwell and approximately 1.3 eV for thermal cycling. This divergence indicates that distinct physical mechanisms dominate under each stress regime. The lower activation energy is consistent with electrically and thermally driven on-die degradation within the FPGA I/O macro, including bias-related aging of output drivers and pad-level structures. In contrast, the higher activation energy observed under thermal cycling is characteristic of diffusion- and creep-dominated thermo-mechanical damage in package-level interconnects, such as solder joints. These findings demonstrate that resistance-based monitoring of FPGA I/O paths can discriminate between device-dominated and package-dominated aging mechanisms, providing a practical foundation for reliability assessment and self-monitoring methodologies in complex electronic systems.