The integration density of state-of-the-art electronic systems is limited by the reliability of the manufactured integrated circuits at a desired circuit density. Design rules, operating voltages, frequencies, and temperatures are precisely chosen to ensure correct product functional operation over its intended lifetime. Thus, in order to obtain the overall performance and functionality bounded by various design and manufacturing constraints, the integrated circuit reliability must be modeled and analyzed at the very beginning of design stages. This paper reviews some of the most important intrinsic wearout mechanisms of MOSFETs (including hot-carrier injection, time-dependent dielectric breakdown, and negative bias temperature instability) and introduces new accelerated-lifetime and SPICE compact models of these wearout mechanisms. Based on these circuit-aging models, a new SPICE reliability simulation approach is proposed and demonstrated with a simplified SRAM design on a commercial 90-nm technology to help designers understand device-failure behaviors, predict circuit reliability, and improve product robustness.

In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.

Silicon Carbide (SiC) and Gallium Nitride (GaN) are revolutionizing power electronics with greater efficiency and durability than Silicon. Nevertheless, their widespread use is limited by reliability challenges, including thermal degradation, defect propagation, and charge trapping, affecting their stability and lifetime. This review explores these reliability issues, comparing empirical and physics-based models for predicting device performance and identifying practical limitations. We also examine strategies to enhance robustness, from material design improvements to advanced testing methods. We propose a demonstrative GaN power circuit topology specifically for demonstrating reliability in real-world conditions. This work highlights key challenges and opportunities in developing more reliable SiC and GaN technologies for future applications.

This work explores the principle of utilizing gallium nitride devices as a gate driver for silicon carbide power devices. As silicon has long reached its performance limits, Wide Bandgap semiconductors such as gallium nitride and silicon carbide have emerged as promising alternatives due to their superior characteristics. However, few publications suggest using a gallium nitride-based gate driver for silicon carbide, high-voltage power devices. Unlike standard voltage source gate drivers, this paper proposes a novel bi-polar current source resonant gate driver topology using gallium nitride transistors as a gate drive circuit for silicon carbide power switching. The driver receives a single input supply and pulsed width modulation signal, producing a high current bi-polar gate driving signal. The gate driver is validated by employing the proposed gate driver to a high-power silicon carbide transistor in a resonant boost converter. The experimental results show that the new gate driver recovers the gate charge wasted energy and provides high performances in varying high voltage loads at a 2.5 MHz switching frequency while reducing the gate losses by 26%.

The power-law time plotting for reliability prediction needs to be reexamined. Until now, most degradation plots in microelectronics reliability analysis assume that the data follow a power-law change in time. The plot is the change in a measured parameter versus the log of time, based on the principle that one can calculate exactly the initial indicator value, S₀, and from that, extrapolate any change in that parameter, ΔS(t), as a power-law with time, t^1/m. The normalized change, ΔS(t)/S₀, relies heavily on a precise value for S₀ such that the calculated power-law exponent, m, may be exaggerated such that extrapolated time-to-fail calculations will be optimistic, even by many orders of magnitude. Also, the extrapolated lifetime may be pessimistic, also by orders of magnitude in time. We show that by transforming the x-axis as the time to a power of 1/m, choosing m by setting the second order of a polynomial curve fit to zero, a more accurate prediction can be achieved with a realistic time to fail given the accelerated testing conditions. We also show how to determine what the correct power of time is using a linear fit to a second-order polynomial. The plotting principles presented here are independent of any physics, rather an empirical focus on how to plot the data according to a power-law in time assumption.