This article presents a multi-input single-inductor multi-output energy-harvesting interface that extracts power from three independent sources and regulates three output voltages. The converter employs the proposed double-conversion rejection technique to reduce the double-converted power by up to 81.8% under the light-load condition and operates in various power conversion modes, including the proposed buck-based dual-conversion mode, to improve the power conversion efficiency and maximum load power. The proposed adaptive peak inductor current controller determines the inductor charging period, and the proposed digitally controlled zero-current detector detects the optimum zero-current point according to the operating mode. The proposed converter achieves a peak end-to-end efficiency of 90.2% and a maximum output power of 24 mW, indicating the improvements of approximately 7.52% and 1.85 times, respectively, compared with those of conventional buck-boost converters.

A high-efficiency charger for low-power thermoelectric energy harvesting with a method for improving the efficiency, which is called the adaptive input ripple (AIR) maximum power point tracking (MPPT) technique, is introduced in this paper. On the basis of the key finding that the end-to-end efficiency $(\eta_{E-E})$ is highly dependent on the amplitude of the input ripple of the charger ( $\Delta V_{IN}$ ) in the low-power region, the proposed AIR MPPT technique adjusts $\Delta V_{IN}$ to maximize $\eta_{E-E}$ . Moreover, the minimum input power that allows the charger to maintain operation is enhanced by the proposed AIR MPPT technique. The proposed charger is implemented with 180-nm CMOS technology. An improvement of 21% in $\eta_{E-E}$ is achieved with the proposed technique. Furthermore, the proposed technique enhances the minimum power by 7.5 μW. The startup power and minimum power of the prototype are 37 and 6 μW, respectively. The maximum $\eta_{E-E}$ is 82%.

This article proposes a continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) energy harvesting interface that extracts power from a thermoelectric generator (TEG), regulates a 0.75-V output load, and manages a 1.2-1.45-V battery. The structure employs the proposed CSCR SC converter to improve the power conversion efficiency up to 7.9% higher than that of the conventional converter. Moreover, the structure utilizes a proposed SC-based pulse frequency modulation (PFM) maximum power point tracking (MPPT) method to extract power from a TEG with an MPPT efficiency above 98.15%. In addition, the proposed interface adopts a flying capacitor sharing scheme for the dual-mode operation of the SC interface to increase both the peak end-to-end efficiency and maximum output power. With a 180-nm CMOS process, the proposed interface achieves a peak end-to-end efficiency of 85.4% and maximum output power of 20.8 mW.

This article presents a high-voltage (HV) dual-input buck converter with a bidirectional inductor current (IL) and a fully integrated maximum power point tracking circuit for triboelectric (TE) energy-harvesting applications. The proposed converter regulates HV inputs through a single shared inductor, and HV inputs can be isolated without using an additional HV protection circuit. In addition, the proposed diode-based HV sampling circuit can accomplish high ac voltage sampling and peak detection to perform the fractional open-circuit voltage method without any external components. Fabricated using a 180-nm bipolar-CMOS-DMOS (BCD) process, the proposed system with a self-manufactured polytetrafluroethylene (PTFE)-based TE nanogenerator can regulate two HV inputs up to 70 V and achieve a power conversion efficiency of 84.7% and an end-to-end efficiency of 75.6%, which are 30.2% and 22.7% better than prior work, respectively.

In this letter, a four-phase hybrid step-up/step-down dc–dc converter with a delay-based zero-current detector (ZCD) is proposed. The proposed power stage operates in step-up or step-down mode depending on the target output voltage. It utilizes hybrid switched-inductor-capacitor and dual-path topologies with multiphase operation to reduce conduction loss due to the dc resistance of the inductor by reducing the rms inductor current ( I_L ). The delay-based ZCD determines the zero-current point of I_L with a five-bit binary signal to compensate for the propagation delay between the control and the output signals of the driver. The system is fabricated using 180-nm CMOS technology. The power density is 1.838 A/mm ² , and the peak efficiency is measured at 89.49% and 86.83% in the step-down and step-up mode, respectively, with a load current range of up to 2 A.