Internet of Things deployments face escalating security threats, yet systematic methods for auditing the defensive posture of IoT device networks remain underdeveloped. Current intrusion detection evaluations focus on algorithmic accuracy while neglecting operational requirements—computational efficiency, reproducibility, and interpretable risk assessment—that security audits demand. This paper introduces a reproducible security audit framework for IoT device networks, demonstrated through systematic evaluation of four machine learning models (Random Forest, LightGBM, XGBoost, Logistic Regression) on the TON_IoT dataset containing nine attack categories targeting smart environments. Our audit methodology enforces strict feature hygiene by excluding identity-revealing attributes, benchmarks both threat detection capability and computational cost, and provides complete reproducibility artifacts including preprocessing pipelines and trained models. The framework evaluates security posture through dual lenses: binary classification (distinguishing compromised from legitimate traffic) and multiclass classification (attributing threats to specific attack types). Binary audit results show ensemble models achieve 99.8–99.9% accuracy with perfect ROC-AUC (100%) and sub-15 ms inference latency per 1000 flows, confirming reliable attack detection. Multiclass auditing reveals more nuanced findings: while overall accuracy reaches 99.0% with macro-F1 near 97%, rare attack types expose critical blind spots—man-in-the-middle threats achieve only 78% F1 despite representing serious security risks. LightGBM provides optimal audit performance, balancing 99.93% detection accuracy with 2.76 MB deployment footprint. We translate audit findings into actionable security recommendations (network segmentation, rate-limiting, TLS metadata collection) and compare against twenty published studies, demonstrating that our framework achieves competitive detection rates while uniquely delivering the transparency, efficiency metrics, and reproducibility required for credible security assessment of production IoT networks.

Elliptic curve cryptography (ECC) combines strong security with short keys, which makes it a good fit for embedded and IoT devices. In these systems, scalar point multiplication is usually the most demanding operation. Published hardware results are hard to compare because researchers work with different platforms, operand widths, and evaluation methods. DSP-free, logic-only implementations of GOST R 34.10-2012 over GF(p), especially those assessed by both cycle count and hardware cost, are uncommon. This work presents an open-source, reproducible RTL implementation and evaluates three architectures under identical conditions at 256 and 512 bits, using neither DSP blocks nor BRAM. Architecture A relies on a direct full-size modular multiplier and serves as a non-viable baseline. Architecture B carries out bitwise Montgomery multiplication, while Architecture C applies a regular LadderStep scheme. All three designs were written in SystemVerilog and checked against a reference software model using 100 test vectors. They were then synthesized on the Tang Primer 20K and Tang Mega 138K FPGAs. Architecture A had the lowest average cycle count, but its performance depended on the input and it exceeded the available resources. Architectures B and C both completed in constant time. Compared with Architecture B, Architecture C used 5.53–5.55× as many cycles, while cutting the Gowin-reported logic-element count by 4.88–7.13× and the flip-flop count by 2.56–3.13×. It also produced a smaller implementation area in the preliminary ASIC-oriented synthesis. That makes Architecture B the stronger option for resource-rich platforms where speed comes first; Architecture C fits better on resource-constrained FPGAs and in compact ASIC designs.