Resilience is one of the key requirements for the future 6G wireless communication networks. The hardware components for the 6G network nodes should be self-aware and self-adaptive, allowing for timely detection of transient and permanent faults, and autonomous system reconfiguration in order to maintain the required functionality even in the case of anomalies. In this work, we present our preliminary design of a resilient processing platform intended to serve as a processing unit in 6G network nodes. The platform integrates a quad-core RISC-V processor, a triple-core neural network accelerator, memory blocks, a variety of on-chip sensors, and a customized controller for fault management and operating mode selection. The prototype of the processing platform has been implemented on a commercial FPGA platform, and the selected use case is the radar-based hand gesture recognition.

This paper presents a performance analysis of three digital multiplier architectures—array, Wallace without carry-look-ahead (CLA), and Wallace with CLA logic—targeted for neural network (NN) accelerators. Simulations were performed using an IHP's 130 nm CMOS standard cell library in Cadence Spectre, focusing on propagation delay and power consumption across different supply voltages, temperatures and transistor dimensions. The Power Delay Product (PDP) was used to evaluate overall efficiency. Results show that the Wallace multiplier without CLA logic and the smallest cells offers the best trade-off in terms of delay and power, making it a strong candidate for low-power, high-performance applications.