The intensity of cosmic radiation may differ over five orders of magnitude within a few hours or days during the Solar Particle Events (SPEs), thus increasing for several orders of magnitude the probability of Single Event Upsets (SEUs) in space-borne electronic systems. Therefore, it is vital to enable the early detection of the SEU rate changes in order to ensure timely activation of dynamic radiation hardening measures. In this paper, an embedded approach for the prediction of SPEs and SRAM SEU rate is presented. The proposed solution combines the real-time SRAM-based SEU monitor, the offline-trained machine learning model and online learning algorithm for the prediction. With respect to the state-of-the-art, our solution brings the following benefits: (1) Use of existing on-chip data storage SRAM as a particle detector, thus minimizing the hardware and power overhead, (2) Prediction of SRAM SEU rate one hour in advance, with the fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions, (3) Online optimization of the prediction model for enhancing the prediction accuracy during run-time, (4) Negligible cost of hardware accelerator design for the implementation of selected machine learning model and online learning algorithm. The proposed design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications, allowing to trigger the radiation mitigation mechanisms before the onset of high radiation levels.

Simulation-based fault injection is a widely used technique for early-stage circuit reliability analysis. However, it consumes significant time, particularly for complex circuits. This paper introduces two Machine Learning (ML) methodologies to predict simulation-based fault injection outcomes at the gate level. The initial approach employs Neural Networks (NNs), extracting structural features from synthesis reports and simulation-related characteristics from Value Change Dump (VCD) waveforms. Nevertheless, NNs are restricted to learning from individual gate attributes. To exploit the comprehensive structure of entire circuits, we propose a method to convert circuits into graphs. This facilitates the utilization of Graph Neural Networks (GNNs) as advanced models, resulting in improved prediction performance. We select six open-source circuits with diverse complexities and functions to validate these methodologies and explore their adaptability across various circuits. Our experiments demonstrate the superior performance of GNNs compared to NNs in terms of prediction accuracy, efficiency in hyperparameter search, and the ability to address imbalanced datasets. Additionally, we investigate the feasibility of deploying the trained models to predict results in new circuits. Based on the experimental outcomes, we present an approach for leveraging the proposed methodology to accelerate simulation-based fault injection.

Nanometer circuits are becoming increasingly susceptible to soft errors. Selective hardening is a less expensive technique to improve the reliability of circuits because it hardens the critical components instead of hardening an entire circuit. One challenge of selective hardening is efficiently and effectively identifying the critical parts in circuits. Simulation-based fault injection is commonly used but extremely time-consuming, especially for complex circuits. This paper proposes an approach based on Graph Neural Networks (GNNs) to identify critical flip-flops in circuits. GNNs can take advantage of the circuit’s structural features and the features of individual flip-flops. To convert the features into abstract data that can be fed into GNNs, we provide a feature extraction method that uses a graph model to represent the relevant features of the circuit. The method converts the target circuit into a graph representing its architecture. The graph also contains features of individual flip-flops extracted from the circuit’s netlist and the Value Change Dump (VCD) waveforms of the test used for fault simulation. Additionally, we extract edge features in the graph to utilize the information on combinational gates on the path between flip-flops. Datasets generated based on two open-source RISC-V cores are used to validate the proposed approach. We compare the performance of different GNNs on them and discuss the contribution of edge features to their performance. Our experiments show that the prediction accuracy increases significantly with edge features. GraphSAGE and SAGE-GCN with edge features perform best among the selected GNNs. The highest accuracy we achieved on Ibex and RI5CY is 97.75% and 98.67%, respectively. We also provide a method to accelerate the process of critical flip-flop identification.

Evaluating the sensitivity of circuits to single event upset (SEU) faults has become increasingly important and challenging due to the growing complexity of circuits. Simulation-based fault injection is time-intensive, particularly for highly complex circuits. This article proposes a novel approach using Spatio-temporal graph convolutional networks (STGCNs) to predict SEU fault propagation results in circuits. By representing circuits’ structure as graphs and integrating temporal features from the simulation workload, STGCNs can learn from these spatio-temporal graphs to identify SEU fault propagation patterns. To validate this method, we test it on six evaluation circuits, achieving a prediction accuracy of 93%–99%. Given this performance, to accelerate SEU simulation-based fault injection, we divide SEU faults into three subsets and use an STGCN fine-tuned on the training and validation dataset to predict SEU fault propagation in the test dataset, eliminating the need for simulation and reducing the required time. To identify an efficient dataset separation method, we compare three sampling methods: 1) spatial sampling (sampling flip-flops for injected faults); 2) temporal sampling (sampling time points for fault injection); and 3) hybrid sampling (incorporating both spatial and temporal sampling). The hybrid sampling approach is the most promising, optimizing the tradeoff between efficiency and accuracy. This approach reduces simulation time by 50% while maintaining accuracy above 95% on the six evaluation circuits.

The solid phase reactions of Ni with GaAs substrates are investigated. The experimental results reveal that the Ni-GaAs solid phase reaction forms a ternary phase of Ni₂GaAs when annealing temperatures are in the range 250–300°C. As the annealing temperature increases to 400°C, the Ni₂GaAs phase starts to decompose due to NiAs phase precipitation. Ni-GaAs alloys processed at 400°C with a 3 min annealing time demonstrate a sheet resistance of 30Ω/square after unreacted Ni removal in hot diluted-HCl solutions. Therefore, Ni-GaAs alloys formed by solid phase reaction could be promising metallic source/drain structures with significant low series resistance for high mobility III—V metal-oxide-semiconductor field effect transistor (MOSFET) applications.