Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

Approximate computing is an attractive paradigm for reducing the design complexity of error-resilient systems, therefore, improving performance and saving power consumption. In this work, we propose a new two-level approximate logic synthesis method based on cube insertion and removal procedures. The experimental results have shown significant literal count and runtime reduction compared to the state-of-the-art approach. The method scalability is illustrated for a high error threshold over large benchmark circuits. The obtained solutions have presented a literal number reduction up to 38%, 56%, and 93% with respect to an error rate of 1%, 3%, and 5%, respectively.

This work shows the soft error robustness of a FinFET Dual Interlocked Cell (DICE) SRAM at 7nm technology. With the voltage scaling, the DICE robustness decreases as expected. Despite that DICE SRAM at hold state shows a high level of soft error immunity, there is a sensibility window for SEU during the read operation. The read operation is the most critical for SEU, and the operation at 0.4V shows a reduction of 58% on the LETth and 33% on the Read Static Noise Margin with similar behavior compared with traditional 6T cell.

Memristive devices are promising building blocks for designing beyond von-Neumann computing applications. In this scenario, memristive material implication is one of the most notable techniques for implementing stateful logic circuits. One of the major drawbacks of this approach is the need to perform lengthy sequences of material implications to synthesize a given Boolean function. However, we show that many of these operations are ineffective and can be dismissed. Based on this assumption, this paper proposes a new implementation method to reduce the length of the sequences. Our proposal uses an auxiliary circuit to predict the necessity to perform each material implication, whose execution is conditioned to its effectiveness. We present the designed circuit and demonstrate its operation through electrical simulations. This work also discusses the results obtained from the analysis of several benchmark functions, in which we observed a reduction of 50 - 90% in the time spent performing this kind of computing.