The inner spacer module, which profoundly affects the final performance of a device, is a critical component in GAA NSFET (Gate-all-around Nanosheet Field Effect Transistor) manufacturing and necessitates systematic optimization and fundamental innovation. This work aims to develop an advanced SiGe etching process with high selectivity, uniformity and low damage to achieve an ideal inner spacer structure for logic GAA NSFETs. For three distinct dry etching technologies, ICP (Inductively Coupled Plasma Technology), RPS (Remote Plasma Source) and Gas Etching, we evaluated their potential and comparative advantages for inner spacer cavity etching under the same experimental conditions. The experimental results demonstrated that Gas Etching technology possesses the uniquely high selectivity of the SiGe sacrificial layer, making it the most suitable approach for inner spacer cavity etching to reduce Si nanosheet damage. Based on the results, in the stacked structures, the SiGe/Si selectivity ratio exhibited in Gas Etching is ~9 times higher than ICP and ~2 times higher than RPS. Through systematic optimization of pre-clean conditions, temperature and chamber pressure control, we successfully achieved a remarkable performance target of cavity etching: the average SiGe/Si etching selectivity is ~56, the inner spacer shape index is 0.92 and the local etching distance variation is only 0.65 nm across different layers. These findings provide valuable guidance for equipment selection in highly selective SiGe etching and offer critical insights into key process module development for GAA NSFETs.

In logic device development, gate-all-around nanosheet field-effect transistors (GAA NSFETs) are widely regarded as the future mainstream architecture. Due to an innovative stacked-channel design, a novel process module of channel release has been introduced, posing significant challenges to device manufacturing. The channel release quality plays a decisive role in the device’s turn-on voltage and operating speed. Meanwhile, the complex interferences are undoubtedly brought by diverse structures and manufacturing thermal budgets of GAA NSFETs. Here, the non-plasma gas etching, which is not yet widely used in the current industry, is adopted for channel release. The influences of nanosheet width, spacing, and annealing conditions on the etching process are systematically studied. A SiGe/Si etching selectivity as high as 87 is achieved. With increasing channel width, a downward trend in the single-sided damage in the central region of Si nanosheets is shown. At >100% over-etching, the Si single-sided damage in structures with different channel spacing is controlled below 1 nm. The intensified diffusion of Ge elements in the SiGe layer and a gradual slowdown of the SiGe etching rate are caused by increasing the annealing temperature. The root mean square (RMS) value of the channel surface roughness is reduced from 0.087 to 0.069 nm by adding the *H radical pretreatment into the process. These findings provide valuable guidance for developing a channel release etching process with high selectivity, low damage, a stable process window, and low fabrication difficulty.