The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si_0.7Ge_0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (I_sub) and punch-through leakage (I_PT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (I_on, I_off), subthreshold swing (SS), RC delay, and gate capacitance (C_gg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (L_rcs) variations. For both device types, larger L_rcs will result in a shorter effective channel length (L_eff), so that the I_on and I_off simultaneously increase. At the constant I_off, the L_rcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger C_gg as a penalty. Secondly, S/D over recess depth (H_rcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less I_off sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both H_rcs and L_rcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible.

Three new sesquiterpenoid derivatives 1, 2, and 3 were isolated from Ferula ferulaeoides. To confirm the structure, compound 2 was also synthesized via a condensation reaction between compound 1 and 2,2-dimethoxypropane. The structures of these three compounds were elucidated by means of spectroscopic and chemical methods. Their antibacterial activity against drug-resistant Staphylococcus aureus strains were evaluated with MIC values in the range of 0.5–128 µg/mL. Compounds 1 and 3 were capable of inhibiting efflux of ethidium bromide using an in vitro assay. The cytotoxicity of the compounds was evaluated on cultured HEK293 cells, and none of them showed toxicity to HEK293 cells at a concentration of 125 µg/mL.

A novel integration scheme of postgate single diffusion break (PG-SDB) has been proposed to enhance channel stress for Si gate-all-around (GAA) nanosheet field-effect transistors (NS-FET), based on TCAD simulations. Compared to conventional SDB and self-aligned SDB (SA-SDB), the proposed PG-SDB scheme implements SDB module after the replacement metal gate (RMG) process, so as to eliminate the stress relaxation to free surfaces. The channel stress has been boosted to +3.5 GPa/−4.7 GPa, for N/P NS-FETs, respectively. As a result, great drive capability as well as N/P current matching has been achieved in the PG-SDB GAA NS-FETs.

This paper reports the dislocation-related photoluminescence (PL) in GeSn films. The GeSn film samples with Sn content of 1%–7.4% were grown on Ge (001) substrates by molecular beam epitaxy at low temperatures. Dislocations at the interface between the GeSn and the Ge buffer layer as well as the threading dislocations throughout the GeSn layer were observed for the annealed samples, but not for the as-grown samples. PL peaks of the annealed GeSn film samples show a significant red shift with increasing Sn content. However, a large energy difference (122 meV) between the PL peak energy and theoretically calculated indirect bandgap energy was found for all the GeSn films with different Sn contents. Furthermore, the PL peak position as a function of temperature could be well fitted by the calculated E _g – T line, indicating that the PL observed in the GeSn films is dislocation-related PL.