In this paper, we demonstrate a comprehensive study of NF₃-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF₃/O₂/Ar gas mixture is used to etch back the SiN film. The impact of the O₂/NF₃ ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O₂ into NF₃/Ar discharge, the selectivity increases sharply, but when the ratio of O₂/NF₃ is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O₂/NF₃ = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

The inner spacer module, which profoundly affects the final performance of a device, is a critical component in GAA NSFET (Gate-all-around Nanosheet Field Effect Transistor) manufacturing and necessitates systematic optimization and fundamental innovation. This work aims to develop an advanced SiGe etching process with high selectivity, uniformity and low damage to achieve an ideal inner spacer structure for logic GAA NSFETs. For three distinct dry etching technologies, ICP (Inductively Coupled Plasma Technology), RPS (Remote Plasma Source) and Gas Etching, we evaluated their potential and comparative advantages for inner spacer cavity etching under the same experimental conditions. The experimental results demonstrated that Gas Etching technology possesses the uniquely high selectivity of the SiGe sacrificial layer, making it the most suitable approach for inner spacer cavity etching to reduce Si nanosheet damage. Based on the results, in the stacked structures, the SiGe/Si selectivity ratio exhibited in Gas Etching is ~9 times higher than ICP and ~2 times higher than RPS. Through systematic optimization of pre-clean conditions, temperature and chamber pressure control, we successfully achieved a remarkable performance target of cavity etching: the average SiGe/Si etching selectivity is ~56, the inner spacer shape index is 0.92 and the local etching distance variation is only 0.65 nm across different layers. These findings provide valuable guidance for equipment selection in highly selective SiGe etching and offer critical insights into key process module development for GAA NSFETs.

In this work, a novel vertical gate-all-around field-effect transistor (VGAAFET) structure is proposed for scaling CMOS technology. Compared to the traditional VGAAFET, the lengths of gate ( ${L} _{g}$ ), spacer ( ${L} _{\text {sp}}$ ), and source/drain ( ${L} _{{\text S}/{\text D}}$ ) are predefined by the Si/SiGe/Si/SiGe/Si epitaxial stacks. Benefiting from the decoupling of the ${L} _{g}$ , ${L} _{\text {sp}}$ , and ${L} _{{\text S}/{\text D}}$ from the contact gate pitch (CGP) in the VGAAFET, the ${L} _{g}$ and ${L} _{\text {sp}}$ have been optimized to enhance the device performance without extending the footprint. To address the structural asymmetry and reduce the parasitic resistance ( ${R} _{\text {para}}$ ) of the VGAAFET, the backside contacts (BSCs) technology is integrated. Compared to the frontside contacts (FSCs) VGAAFET, the bottom source/drain resistance ( ${R} _{\text {BotS}/\text {D}}$ ) is reduced by 46.5%, and the on-state normalized current ( ${I} _{\text {on},\text {norm}}$ ) is increased by 21.8% for BSC-VGAAFET. Additionally, by employing the extension region doping (ERD) technology to improve the electrical characteristics symmetry between n/p VGAAFETs, an enhanced n/p current ratio from 1.31 to 1.16 has been achieved. Furthermore, to benchmark the power, performance, and area (PPA) characteristics between the VGAAFET and lateral GAAFET (LGAAFET) at the circuit-level, the nand2 standard cells are designed at the same footprint, and evaluated in our design technology co-optimization (DTCO) platform. The results of the 15-stage ring oscillator (RO) demonstrate that at the same supply voltage ( ${V} _{\text {dd}}$ ) and footprint, the BSC-VGAAFET achieves 52.2% frequency improvement and 21.6% energy-delay product (EDP) reduction compared to the LGAAFET. Therefore, the BSC-VGAAFET is a promising transistor architecture for next-generation integrated circuits (ICs).

Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption. However, the lack of effective doping methods for 2D semiconductors remains a significant challenge, impeding the realization of homogeneous complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs). Here, we report the monolithic integration of wafer-scale homogeneous top-gated WSe₂ CMOS circuit arrays. The p-type and n-type doping methods could effectively modulate carrier polarity and concentration for WSe₂, enabling the fabrication of wafer-scale CMOS inverter arrays via a proposed bilayer hard mask process. A representative CMOS inverter exhibits a voltage gain of up to 396 V/V, with a low static power consumption of ~ 30 pW and a noise margin exceeding 90%. Furthermore, more complex CMOS circuits, like XOR and a multiplexer (MUX), are successfully fabricated. This demonstration of homogeneous CMOS integration shows a promising strategy for the practical deployment of 2D semiconductors in low-power large-scale ICs.

In logic device development, gate-all-around nanosheet field-effect transistors (GAA NSFETs) are widely regarded as the future mainstream architecture. Due to an innovative stacked-channel design, a novel process module of channel release has been introduced, posing significant challenges to device manufacturing. The channel release quality plays a decisive role in the device’s turn-on voltage and operating speed. Meanwhile, the complex interferences are undoubtedly brought by diverse structures and manufacturing thermal budgets of GAA NSFETs. Here, the non-plasma gas etching, which is not yet widely used in the current industry, is adopted for channel release. The influences of nanosheet width, spacing, and annealing conditions on the etching process are systematically studied. A SiGe/Si etching selectivity as high as 87 is achieved. With increasing channel width, a downward trend in the single-sided damage in the central region of Si nanosheets is shown. At >100% over-etching, the Si single-sided damage in structures with different channel spacing is controlled below 1 nm. The intensified diffusion of Ge elements in the SiGe layer and a gradual slowdown of the SiGe etching rate are caused by increasing the annealing temperature. The root mean square (RMS) value of the channel surface roughness is reduced from 0.087 to 0.069 nm by adding the *H radical pretreatment into the process. These findings provide valuable guidance for developing a channel release etching process with high selectivity, low damage, a stable process window, and low fabrication difficulty.

Cryogenic CMOS technology provides a promising approach to surpass the Boltzmann limit and advance Moore’s Law, addressing the increasing demand for high-performance computing. However, at cryogenic temperatures, the subthreshold swing (SS) of the device saturates due to the band-tail effect. This study presents a 3-vertically stacked gate-all-around nanosheet (NS) transistor featuring room-temperature O radical interface passivation. This approach leverages the high reactivity of O radicals to minimize etch-induced damage, passivate interface defects, reduce thermal budget, and ensure uniformity in complex 3D structures. Structural characterization revealed a uniform 0.76-nm-thick interface layer, with a surface roughness of 0.103 nm and an interface trap density of 2.72 × 10¹¹ cm⁻²·eV⁻¹ at 300 K. Thereby, the band-tail-induced SS saturation at cryogenic temperatures is effectively mitigated. Experimental results confirm a lower characteristic temperature T_v for reaching the saturation plateau, and a saturated SS of 15.4 mV/dec at 4.5 K. Furthermore, reducing disorder-induced defects substantially suppresses the band tail state-assisted carrier emission, thereby minimizing subthreshold leakage. This enables the device to achieve an off-state current below 1 pA/μm at a temperature under 77 K, reaching 0.18 pA/μm at 4.5 K. Additionally, a reduction in 25.4% in drain-induced barrier lowering (DIBL), with a 9% boost in transconductance (G_m) peak is achieved at 4.5 K. The enhanced subthreshold switching, reduced leakage, and improved G_m in this interfacial-optimized NS FET strongly supports cryo-CMOS as a viable solution for energy-efficient computing.