In this work, using the high-throughput density functional theory calculation method, the influence of 36 alloying elements on the elastic properties of FCC-Cu was systematically studied, and based on the Labusch model, a linear relationship was fitted between the composition and lattice parameters, and the shear modulus. The solid solution strengthening behavior brought about by alloying was studied quantitatively. The results showed that most alloying elements have solid solution potentiality in copper. The change in the elastic modulus and the strengthening effect of alloying on solid solutions were determined by the elements’ positions in the periodic table. In the same period, the alloying elements located in the middle of the period tended to enhance the elastic modulus of copper, while the elements located at both ends have greater solid solution strengthening ability. The predicted results are in good agreement with the experimental values, which provide theoretical guidance for the design of high-performance copper alloys.
The GeTe monolayer possesses an AB binary buckled configuration, which can induce intrinsic Rashba spin splitting due to the existence of an internal electric field. However, the electronic structure obtained shows that these splittings are not present near the Fermi level, which makes it unsuitable for practical application. Based on first-principles calculations, we introduce strain engineering to manipulate the Rashba effect. Our results suggest that tensile strain can induce a remarkable Rashba spin splitting of valence band maximum (VBM). With a tensile strain of 10%, the Rashba coefficient can increase to ∼2 eVÅ, which is larger than most 2D Rashba materials. This is because the tensile strain converts the orbital component of the VBM from Te-px (Te-py) to Te-pz states. We propose a spin transistor based on the GeTe monolayer according to its Rashba effect and tunability under strain. Compared to conventional spin field-effect transistors, this transistor can achieve a shorter channel length at the nanometer level, which means that a chip can contain more transistors and integrate it into nanodevices with higher density.