Spiking Neural Networks (SNNs) have emerged as an essential paradigm for brain-inspired computing, achieving superior energy efficiency on neuromorphic hardware. However, as network scale increases, SNNs encounter growing challenges in deployment efficiency. While structured pruning provides a practical approach, existing methods typically rely on a dense-to-sparse training pattern, which incurs high memory overhead during training and fails to exploit the efficiency of sparse computation from the outset. There is a lack of effective frameworks that enforce structured sparsity within a sparse-to-sparse training regime for SNNs. To bridge this gap, we propose the Channel Dual-phase Sparsity (C-DPSS) framework. This approach leverages Dynamic Sparse Training (DST) to enable efficient topology exploration while progressively enforcing hardware-friendly structured sparsity. Our methodology is grounded in the empirical observation that channel-level neuronal activity patterns stabilize significantly earlier than synaptic weights during training. Motivated by this temporal discrepancy, C-DPSS employs a dual-phase saliency metric during training. It defines an early exploration phase dominated by neuronal dynamics, and smoothly transitions to a late refinement phase driven by synaptic efficacy. Extensive experiments on both static and neuromorphic benchmarks demonstrate that C-DPSS provides a robust accuracy-efficiency trade-off. Notably, for VGG-16 on CIFAR-10, our method achieves a 50% channel sparsity and a 42% decrease in Synaptic Operations (SOPs) with no accuracy loss, outperforming state-of-the-art static structured pruning methods. Furthermore, we validate the scalability of our approach by providing a feasibility demonstration of sparse-to-sparse structured pruning on the ImageNet-1K. Our code is available at: https://github.com/JunLi0514/C-DPSS.

The energy efficiency of object detection processors based on traditional artificial neural networks (ANNs) is constrained by intensive multiply-accumulate operations and frequent memory accesses. Spiking neural networks (SNNs), characterized by biological plausibility, multiplier-free computation, and inherent sparsity, offer a promising alternative for energy-efficient inference. However, deploying SNNs for high-resolution object detection faces three key challenges: 1) long time-steps to maintain accuracy; 2) redundant weight access across time-steps; and 3) substantial external memory access (EMA) incurred by intermediate feature maps (FM). To address the above challenges, a dedicated SNN processor is presented with three contributions: 1) a customized short time-step quantized spiking YOLO (QS-YOLO) model, achieving 65.80-72.90% mAP on VOC2007 within only 1–4 time-steps through a progressive temporal compression (PTC) and quantization framework; 2) a novel weight-locally-distributed stationary spatio-temporal sequential interleaving (WLS-STS) dataflow, enabling single weight access across all time-steps while supporting flexible time-step configuration without loss of processing element (PE) utilization; and 3) a workload-aware dynamic global buffer allocation strategy to eliminate FM-EMA. The proposed processor incorporates a heterogeneous dual-core architecture, comprising a spike-driven accumulate unit (SAU) and a multiply–accumulate unit (MAU), to efficiently accelerate both spiking and non-spiking operators in QS-YOLO. Implemented on XCVU13P FPGA, the processor achieves a peak energy efficiency of 146.48 GOPS/W at 100MHz. Compared with existing object detection FPGA processors, the proposed processor achieves state-of-the-art energy efficiency.

The hardware power-aware keyword spotting (KWS) implementation requires small memory footprint, low-complex computation, and high accuracy performances. Binary neural networks (BNNs) naturally satisfy these constraints. They quantize both weights and activations to 1-bit. This reduces storage and replaces most multiply–accumulate operations with bitwise operations. However, such extreme quantization incurs substantial information loss and leaves a noticeable accuracy gap relative to full-precision models. Optimization is also more difficult because the sign function is non-differentiable, and surrogate-gradient updates introduce gradient mismatch. To preserve the hardware benefits of BNNs while alleviating the accuracy degeneration induced by 1-bit quantization, this article addresses the problem from two complementary aspects: Firstly, a Stepwise Self-Knowledge Distillation (SSKD) training approach is proposed to effectively improve the student BNN’s accuracy performance. The SSKD training framework achieves effective supervision for student BNNs. A Stepwise Training Strategy is proposed to optimize the training stability and accuracy. Weight Scaling Factor improves the student’s representational capability. Secondly, an extremely lightweight Binary Temporal Convolutional ResNet (BTC-ResNet) is also proposed. The parameters and calculations inside the network are greatly reduced for the inference. Experiments on the GSCD v1 and GSCD v2 benchmarks demonstrate the effectiveness of our methods for low-power keyword spotting. For the 12-class task, BTC-ResNet14 achieves 97.23% accuracy on GSCD v1 and 97.31% on GSCD v2 with 0.75 Mb parameters and 1.35 M FLOPs. For the 35-class task on GSCD v2, it reaches 95.56% accuracy with 0.76 Mb parameters and 1.35 M FLOPs. These results indicate that our method achieves a competitive accuracy–efficiency balance relative to recent distillation-based BNN KWS baselines reported in the comparative experiments. All these studies are helpful and promising for future KWS deployment on low-power hardware devices.