Hyper-Dimensional Computing (HDC) is an efficient learning paradigm inspired by the high-dimensional properties of human brain. However, existing HDC architectures require large storage overhead to store position and level hyper-vectors, increasing the chip area while also limiting the expansion of dimensions. To solve this problem, we propose a lightweight HDC architecture with Zero Rom overhead, named as ZRHDC. Utilizing a novel parallel encoding method and a rapid random vector generation mechanism based on Linear Feedback Shift Register and shift-flip operations, ZRHDC accelerates encoding process and completely eliminates the ROM overhead. The proposed architecture supports classification tasks with up to 32 categories, 1024 features and 8192 dimensions, achieving 2- $8 \times $ dimensional expansion compared to the state-of-the-art ASIC designs and accuracy improvement in various tasks and training strategies. Moreover, our chip only costs 0.66mm2 at 55nm, achieving 3- $6 \times $ area scaling down. Simulation results show that it consumes 0.771mW when performing the EMG hand-gesture recognition task and merely 0.009mW in standby.

Unstructured pruning introduces significant sparsity in deep neural networks (DNNs), enhancing accelerator hardware efficiency. However, three critical challenges constrain performance gains: 1) complex fetching logic for nonzero (NZ) data pairs; 2) load imbalance across processing elements (PEs); and 3) PE stalls from write-back contention. This brief proposes an energy-efficient accelerator addressing these inefficiencies through three innovations. First, we propose a Cartesian-product output-row-stationary (CPORS) dataflow that inherently matches NZ data pairs by sequentially fetching compressed data. Second, a multilevel partial sum reduction (MLPR) strategy minimizes write-back traffic and converts random PE stalls into manageable load imbalance. Third, a kernel sorting and load scheduling (KSLS) mechanism resolves PE idle/stall and achieves PE array-level load balancing, attaining 76.6% average PE utilization across all sparsity levels. Implemented in 22-nmCMOS, the accelerator delivers $1.85\times $ speedup and $1.4\times $ energy efficiency over baseline and achieves 25.8 TOPS/W peak energy efficiency at 90% sparsity.

Synthetic Aperture Radar (SAR) ship detection is critical to a wide range of maritime applications. Traditional artificial neural networks (ANNs) achieve high detection performance but incur substantial energy consumption, limiting their deployment on edge devices. In contrast, brain-inspired spiking neural networks (SNNs) offer energy-efficiency benefits. Moreover, attention mechanisms can strengthen ship feature representation and suppress background noise in SAR imagery, thereby improving detection accuracy. Motivated by these observations, we propose ESA-YOLO: an energy-efficient spiking attention–based YOLO network for SAR ship detection. First, ESA-YOLO adopts a spike-driven paradigm relying on sparse additive operations to effectively reduce energy consumption. Second, it integrates a spiking attention mechanism. This module captures content-dependent global interactions and long-range context, improving detection performance. Experiments on the HRSID dataset confirm ESA-YOLO’s energy efficiency for SAR ship detection. The results also show that SNNs can be deployed on neuromorphic hardware such as the Wentian chip to reduce energy consumption.