This paper presents the design and experimental characterization of two lock-in amplifier (LIA) prototypes integrated in a 0.18-μm CMOS process with a single supply voltage of 1.8 V. As opposed to previously reported integrated LIAs, synchronous rectification is performed in the current domain, providing key features such as low power (<;420 μW) and reduced area (0.013 mm ² ), with a dynamic reserve better than 35 dB and less than 5% relative error in the signal recovery. The principle of operation of each prototype is presented and their performance is compared with previous implementations, validating their suitability for low-cost portable applications.

Autonomous and semiautonomous mobile robots play an important role in making tasks in environments considered hostile or dangerous for a human being. In order to execute many of the required tasks, robots need, in its architecture, a module of navigation with an appropriate path planning algorithm. This paper presents the development and implementation of a methodology for path planning of a mobile robot using a spherical algorithm and homotopy continuation methods (HCMs). The first section is a brief introduction about HCMs. Subsequently, the homotopy path planning method and spherical path tracking algorithm are explained, as well as the upgraded version and its main features. Then, the main contributions of this paper are presented and the effectiveness of the proposed method is proved. Besides, numerical examples, implementation results in multiple platforms including a 32b microcontroller and robot operating system, are displayed. Finally, some favorable results from a comparative between the proposed methodology against sampling-based planners using the open motion planning library are presented.

This paper presents a new first-order temperature compensated CMOS current reference. To achieve a compact architecture able to operate under low voltage with low power consumption, it is based on a self-biasing beta multiplier current generator. Compensation against temperature is achieved by using instead of an ordinary resistor two triode transistors in parallel, acting as a negative and a positive temperature coefficient resistor, that generate a proportional to absolute temperature and a complementary to absolute temperature current which can be directly added to attain a temperature compensated current. Programmability is included to adjust the temperature coefficient and the reference current magnitude over process variations. Results for a 0.18 μm CMOS implementation show that the proposed 500 nA reference operate with supplies down to 1.2 V accomplishing over a (-40 to +120°C) range temperature drifts below 120 ppm/°C.

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.

This paper presents a new micropower analog lock-in amplifier (LIA) suitable for battery-operated applications thanks to its reduced size and power consumption as well as its operation with single-supply voltage. The proposed LIA was designed in a 0.18 µm CMOS process with a single supply voltage of 1.8 V. Experimental results show a variable DC gain ranging from 24.7 to 42 dB, power consumption of 417 µW and integration area of 0.013 mm². The LIA performance was demonstrated by measuring carbon monoxide concentrations as low as 1 ppm in dry N₂. The experimental results show that the response to CO of the sensing system can be considerably improved by means of the proposed LIA.

Two strategies to enhance transistor performance in SOI technology without increasing the operating voltage are compared. The first option is the use of the self-cascode transistor, a series connection of two conventional FD SOI MOSFETs which, with an appropriate choice of sizes, work as a single transistor with reduced output conductance. The second option is the use of the graded-channel (GC) SOI MOSFET, consisting of a modification of the fully-depleted (FD) SOI MOSFET which leads to better performance of the device in saturation. The paper shows the existing analogy between the operation of self-cascode and GC SOI transistors. The comparison between both strategies is carried out on the basis of simulations with the University of Florida SOI (UFSOI) model and experimental measurements. The area consumed by a self-cascode SOI transistor is estimated to be 10 times larger than that of a GC SOI transistor for the same improvement in output conductance. Experimental results validate the model used for the GC SOI device and also provide numerical quantification of output resistance increase in both configurations.