Recent years have seen fast advances in neural recording circuits and systems as they offer a promising way to investigate real-time brain monitoring and the closed-loop modulation of psychological disorders and neurodegenerative diseases. In this context, this tutorial brief presents a concise overview of concepts and design methodologies of neural recording, highlighting neural signal characteristics, system-level specifications and architectures, circuit-level implementation, and noise reduction techniques. Future trends and challenges of neural recording are finally discussed.

The input-referred noise (IRN) is one of the most crucial performance indicators for the analog front-end (AFE) of neural recording devices. In this study, we present a novel design approach for a low-noise amplifier (LNA) based on the transistor optimization method in CMOS technology. Because flicker noise is predominant in neural recording applications, AFE has been designed to meet input-referred flicker noise specifications, whereas thermal noise contributions are monitored and controlled by flicker noise corner frequencies. Transistor optimization is accomplished using a lookup table that encapsulates its performance based on its current density. Initially, transistors are optimized based on the flicker noise performance; later, they may be further optimized based on their size, power consumption, transconductance, or thermal noise contribution. The proposed approach was validated by designing a folded-cascode amplifier with IRN ranging from 2 to 8 $\mu \text{V}_{\text {rms}}$ . The results of the simulation show that the errors of our design methodology are less than 10%, which is less than those of the $g_{m}/I_{D} $ and inversion coefficient methods. The proposed LNA achieves 2.1 $\mu \text{V}_{\text {rms}}$ while consuming 0.83 $\mu \text{W}$ from a 1.2 V supply.

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is flowing through the device. Using such an approach reading the state and its adjustment are done simultaneously, which reduces the programming latency. In the proposed method, instead of tuning the memristance, the state of the memristor will be set to the desired value, which is proportional to a control voltage. The low programming latency, six-bit accuracy, and use of a simple circuit for programming, are the main advantages of our solution. The proposed circuit is designed and laid out in 0.35 µm CMOS technology and takes 0.0273mm². Furthermore, the proposed approach is applied to a memristor emulator to demonstrate its correct operation in real applications.

An asymmetric memristive device fabricated with a titania (TiO_x)-based switching layer deposited through atomic layer deposition with a thickness of ∼37 nm was investigated. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy coupled with energy-dispersive x-ray spectroscopy were employed for device structural characterization. A unipolar resistive switching behavior (both at positive and negative voltages) was observed through the memristor’s current–voltage characteristics. A remarkably smaller forming voltage (from the top Pt electrode to the grounded Au electrode) of 0.46 V was achieved, while it approached (positive bias from the Au electrode and holding Pt electrode as grounded) 0.25 V, which is a much smaller forming voltage than has ever been reported for titanium-based oxides without doping. The retention and endurance characterization over 2000 switching cycles were satisfactory without degradation.

This paper introduces a novel compact memristor model that encompasses various phenomena such as linear and nonlinear dopant drifts, exponential drifts of dopants in high electric fields, asymmetry in the on and off switching, and threshold effects. This model simplifies its structure by eliminating the window function and integrating its functionality through varactor-based integrators, thus avoiding convergence issues caused by the feedback loop within the conventional models. It demonstrates improved accuracy compared to previously proposed models, achieving more than 10% accuracy improvement compared to other models for some devices (e.g., reducing error from 15.2% to 4.3%). In addition, experimentation was conducted on a commercially procured memristor, where the model was aligned with the obtained test outcomes. Subsequently, a TiO₂ device was fabricated, and the model was correspondingly adjusted to align with the outcomes from its tests. Experimental results show that the model achieves 98% accuracy in modeling the commercially available device and 97% in modeling the fabricated device.