Spike-timing dependent plasticity (STDP)-based spiking neural network (SNN) is a promising choice to realize unsupervised intelligent systems with a limited power budget. In addition to STDP, another two bio-inspired mechanisms of lateral inhibition and homeostasis are always implemented in the unsupervised training procedure of STDP-based SNNs. However, the existing methods to achieve lateral inhibition necessitate a great number of connections that are proportional to the square of the number of learning neurons, and the existing hardware solution of homeostasis demands complex circuits for each learning neuron, both of which challenge the hardware implementation of STDP-based SNNs. In this paper, we propose a novel SNN using memristor-based inhibitory synapses to realize the mechanisms of lateral inhibition and homeostasis with low hardware complexity. The proposed SNN can improve the network scalability by reducing the connection number for lateral inhibition from N2 to N and reduce the hardware overhead by leveraging the circuit of lateral inhibition to achieve homeostasis. Software simulations on the recognition task on MNIST dataset show that the proposed SNN achieves a ∼2 times higher learning efficiency with comparable accuracy. In addition, the challenging properties of realistic memristor devices, including limited number of resistive states, intrinsic parameter variation, and permanent open device, are added in the simulation to evaluate the robustness of our proposed approach.

Neuromorphic processors have gained momentum recently due to their high energy efficiency in artificial intelligence applications compared to DNN accelerators. Most neuromorphic processors are executing SNNs (Spiking Neural Networks). Liquid State Machine (LSM), as the spiking version of reservoir computing, shows advantages and great potential in image classification, speech recognition, language translation, etc.. Comparing with other SNN models, LSM has the characteristics of easy to train and low resource utilization, which is suitable for low-power and resource-constrained edge computing scenarios. In this paper, we propose a novel design of a neuromorphic processor, LSMCore, aiming at LSM acceleration. LSMCore supports both training and inference of LSM. It consists of 256 input neurons, 1024 liquid neurons, and 1.31M synapses. Besides, multiple optimization techniques, including weight quantization for reducing storage, zero-skipping for decreasing dynamic sparsity, and mini-batch training are adopted in this processor. The experimental results show that the frequency of LSMCore achieves 400 MHz, the power is 4.9W and the area is 18.49 mm ² with a 40nm library. Comparing with the baseline, LSMCore achieves up to $80.7\times $ ( $49.6\times $ ), $91.3\times $ ( $56.3\times $ ), and $83.1\times $ ( $56.8\times $ ) speedup on MNIST, N-MNIST, and Free Spoken Digital Dataset (FSDD) respectively for training (inference), while the accuracy of LSMCore on these three datasets are 96.8%, 97.6%, and 90% respectively.

The traffic patterns of spiking neural networks (SNNs) exhibit high variability and stochastic, leading to the emergence of elevated traffic hotspots on the network-on-chip (NoC)-based neuromorphic processors. Predicting the occurrence of hotspots remains one of the most challenging issues in NoC design. This article presents the first attempt toward traffic hotspot prediction by utilizing liquid state machine (HP-LSM). The predictor extracts essential information reflecting the current state of the NoC to predict potential routing hotspots in the subsequent time step. Furthermore, we designed the hardware architecture for HP-LSM, which incorporates leaky-integrate-and-fire (LIF) neurons with configurable biological parameters. Meanwhile, we introduce a novel hotspot-aware path-based multicast (HaPM) routing algorithm that utilizes advanced knowledge acquired from HP-LSM to guide packet routing throughout the network, aiming to improve the performance of NoC. Results indicate that the HP-LSM can forecast hotspot formation with an accuracy up to 89.36% and 90.19% for two spiking-based datasets, respectively. The hardware experiment results demonstrate a 92.03% reduction in the average execution time of zero skipping compared with nonzero skipping. Moreover, the HP-LSM exhibits a reduction of up to 79.30% in the number of neurons compared with other related SNN predictor models. The experiments reveal a reduction of 73.67% and 53.42% in the average length of the multicast path when compared with dual-path (DP) or multipath (MP) multicast routing. The HaPM demonstrates improved performance in terms of average latency and throughput compared with DP, MP, and path-based multicast (PbM) multicast routing.

Neuromorphic computing based on spiking neural network (SNN) shows good energy-efficiency. However, the conventional convolution operation required in processing the output of the frame-based vision sensor makes SNN inefficient because the convolution requires full-image processing. Frameless vision sensors (also called event-based vision sensors) can address this problem because they produce spikes only when events occur in the image. The image encoding of frameless vision sensors is Address Event Representation (AER), an emerging asynchronous protocol. AER events are particularly well-suited for SNN processing. Indeed, computation and communication in SNN are asynchronous because of the asynchronous nature of AER events. This paper presents an SNN hardware inference engine based on an asynchronous Processing Element (PE) array with AER events as input. The engine uses a convolution algorithm based on AER events. This design also uses distributed storage in the PE array to reduce the cost of memory access. The experimental results show that the design can achieve a recognition accuracy of 97.5% for the MNIST AER dataset. This design reduces by 9 the computing activity compared to a baseline systolic array based accelerator.