In this brief we propose a technique to compensate the distortion of an open-loop VCO-based ADC. The VCO is linearized by placing an analog feedback loop based on a frequency-to-current converter which uses an asynchronous switched capacitor circuit. The feedback loop relies on the VCO gain to linearize the ADC without requiring additional amplifiers. This permits the use of a ring oscillator with small input range to efficiently encode a large signal. The proposed technique has been experimentally demonstrated in an audio ADC. The proof-of-concept chip was fabricated in 130nm CMOS and achieves 76.64 dBA of peak SNDR with a Dynamic Range of 90dB and a power consumption of 482 $\mu \text{W}$ in 20kHz.

One of the limitations of conventional VCO-ADCs is the restriction to first-order noise shaping. True VCO-ADC architectures have been proposed to increase the noise-shaping order by cascading several VCO integrators, but without requiring analog feedback loops. A high noise-shaping order allows to reduce the input VCO frequency compared to a conventional VCO-ADC with similar dynamic range, which improves power consumption. Prior-art True VCO-ADC architectures represent state variables either with a unity-weighted code or with a single-bit. Unity-weighted encoding is a natural choice when ring oscillators are selected as loop filter integrators. However, chip area restrictions force unity-weighted state variables to have few levels. A reduced number of levels in the state variables limits the dynamic range of True VCO-ADCs. In this paper, we experimentally demonstrate a second-order audio VCO-based ADC that uses ring oscillators as integrators but employs Gray and binary encoded state variables. As a consequence, the complexity and area of the True VCO-ADC architecture is reduced, breaking the barrier that limits the dynamic range of prior designs. The proof-of-concept chip shows a dynamic range of 103 dB achieving a peak SNDR of 76.5 dB-A with a power of 250 $\mu$ W occupying 0.095 $\text{mm}^2$ in 130 nm CMOS.

This paper presents the experimental results of a LIF neuron based on time-domain analog circuitry. This kind of neuron is the core of spiking neural networks (SNN) used in edge applications. Edge applications require power-efficient neuron designs whose power consumption is extremely low when idle, and low when in dynamic operation. The proposed neuron complies with the aforementioned requisites by transforming the voltage-based threshold of conventional LIF neurons into a time domain threshold on a quadrature oscillator. In conjunction with a charge-sharing integrator, the proposed neuron shows a energy efficiency of 201fJ/SOP implemented 0.13μm process.

Analog to Digital Converters based on Voltage Controlled Oscillators are assumed very tolerant to sampling clock inaccuracies. This is due to the first-order shaping of sampling-induced errors, which appear indistinguishable from VCO phase quantization errors. A closer look to VCO-ADCs reveals that jitter errors can be problematic under different kinds of inputs and are affected by circuit impairments. This paper theoretically analyzes the behavior of pseudo differential open-loop VCO-ADCs in the presence of clock jitter and provides simulations of practical cases. In spite of being noise-shaped, the error induced by jitter is shown to depend on the input signal power. In-band noise degradation due to out-of-band signal interferers is also described. Finally, we compare open-loop and closed-loop VCO-ADCs with respect to their robustness against clock jitter.

A key component of VCO-ADCs is the ring oscillator, which determines the circuit and quantization noise of the converter. The input-referred thermal and flicker noise of a VCO-ADC stems from the VCO driver source and the VCO phase noise. On the other hand, quantization noise depends on the oscillation frequency of the VCO with respect to the sampling frequency. An optimal VCO-ADC design should balance oscillation frequency with flicker and thermal contributions of the VCO. In this paper, we show a simple modification of the conventional stages used in VCO-ADC ring oscillators. The modification consists of including two extra transistors in series, isolating the inverter from the power rails when switching. This modification allows one to significantly increase the oscillation frequency while having similar phase noise contributions compared to other ring oscillator architectures with the same area and power.

This manuscript presents two approaches to improve the temperature effects on ring oscillators used in open-loop VCO-ADCs. The first approach is a circuit design optimization, which is based on an analysis of the ring oscillator against temperature, considering both gain and frequency deviations. It is shown that ring oscillators can be biased in regions with stable frequency or gain. The second technique is an oscillator stabilization circuitry for differential VCO-ADCs. We propose a common-mode feedback circuit that tracks the VCO frequencies to tune the common bias point. Therefore, intrinsic VCO variations are also compensated by this feedback. A proof of concept chip demonstrating both techniques has been implemented in $0.13\mu $ m. The chip measurements show a frequency and gain drift of 6% and ±0.25dB respectively between -40°C to 100°C. These measurements are comparable to the results achieved by digital temperature calibration without requiring an on-chip temperature sensor.