This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with active feedforward for simultaneous current and noise reduction. By employing an active feedforward stage in the main path, the current dissipation and the thermal noise are effectively suppressed, while the noise and distortion cancelation properties of CG-CS topology are preserved. Moreover, no extra noise is introduced since the additional g _m -boost amplifier follows the same noise-canceling (NC) principle as the CG amplifier, and its noise can be fully canceled at the output theoretically. Thus, the proposed LNA benefits from the g _m -boosting and NC technique simultaneously to obtain a good tradeoff between gain, noise figure (NF), and power consumption. Fabricated in standard 40-nm CMOS technology, the measured results show the proposed LNA exhibits a peak gain of 17 dB, NF of 3.5-5.5 dB from 1 to 11 GHz and an IIP3 of -2.8 dBm at 6 GHz. It consumes 9 mW from a 1.2-V supply and occupies a very compact die area of 0.061 mm ² .

This article presents a leakage-based digital temperature sensor with reduced supply sensitivity for on-chip thermal management. The sensor, featured with a novel supply sensitivity suppression mechanism, performs the temperature-to-frequency conversion by a leakage-dominated ring oscillator (LDRO) with exponential temperature dependence. Thanks to the proposed robust and reconfigurable Schmitt-trigger-based delay cell, both NMOS and PMOS leakage-based sensors can be evaluated in a single design. Fabricated in a standard 55-nm CMOS digital process, the proposed digital temperature sensor occupies a silicon area of only 1770 μm² and can operate under a supply ranging from 0.8 to 1.3 V, with the supply sensitivities of 2.53-5.22 °C/V and 2.84-5.76 °C/V in two working modes at room temperature, respectively. Measurement results show that the sensor achieves an inaccuracy of ±0.70 °C (3σ) from -40 °C to 125 °C after two-point calibration.

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1 dB) at 9 GHz from -12.2 to -5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 x 0.68 mm² area excluding pads and consumes 75 mW.

This article presents a four-element 7.5-9-GHz phased-array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes all the input elements to maximize the beamforming gain. To realize a low-power and compact design, the multielement multibeam phased-array architecture features the gm-based variable-gain phase shifter (VG-PS) and the current-sharing active combiner. The VG-PS with 6-bit phase resolution achieves <; 2° root mean square (rms) phase error and <; 0.3 dB rms gain error at the maximum gain setting. The receiver demonstrates a 20-dB power gain, a 3.6-dB noise figure (NF), and a -19-dBm input 1-dB gain compression point (IP1dB) at 7.5-9 GHz for each element. The chip occupies $5.42\times3.62$ mm ² area excluding pads and consumes 860 mW, equivalent to the record low 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.

This article presents a 7-bit wideband passive attenuator with low insertion loss (IL) and high attenuation accuracy in 55-nm CMOS technology. The π-type and bridge-T-type attenuation units utilize an effective capacitive compensation technique, whose bandwidth extension mechanism is detailed in a single-unit pole-zero analysis. The matching-induced performance deterioration is investigated to minimize amplitude and phase errors at the chip level. The fabricated attenuator demonstrates a 32.4-dB attenuation range with a 0.255-dB resolution and a 3.5-8.4-dB IL from dc to 32 GHz. The measured root-mean-square (rms) amplitude and phase errors are below 0.32 dB and 5.33°, respectively. The attenuator occupies a 0.054-mm ² core area and consumes negligible power.

In this paper, a smart CMOS temperature sensor with a versatile readout scheme is presented. A digital-assisted readout solution is proposed to improve the compatibility of the circuit and maintain the performance of a traditional smart temperature sensor. In addition, the potential multi-operating points of the analog front-end are analyzed, and a compact start-up circuit is designed to make the analog front-end work properly. Fabricated in a standard 0.13 μm CMOS process, the proposed temperature sensor occupies a silicon area of 0.29 mm ² and draws a current of 95 μA from a 2 to 3.6 V supply voltage at the room temperature. Measured results show that the proposed design has the inaccuracy of ± 0.47 °C (3σ) from -40 °C to 125 °C after a single-point temperature calibration. It achieves a resolution of 16 mK at a conversion time of 5.12 ms and a supply sensitivity of less than 0.05 °C/V. Thanks to the versatile readout scheme, the proposed temperature sensor is compatible with multi-sensor systems where the readout-circuitry can be shared between different input signals.