This article proposes a novel wideband common-gate (CG) common-source (CS) low-noise amplifier (LNA) with active feedforward for simultaneous current and noise reduction. By employing an active feedforward stage in the main path, the current dissipation and the thermal noise are effectively suppressed, while the noise and distortion cancelation properties of CG-CS topology are preserved. Moreover, no extra noise is introduced since the additional g _m -boost amplifier follows the same noise-canceling (NC) principle as the CG amplifier, and its noise can be fully canceled at the output theoretically. Thus, the proposed LNA benefits from the g _m -boosting and NC technique simultaneously to obtain a good tradeoff between gain, noise figure (NF), and power consumption. Fabricated in standard 40-nm CMOS technology, the measured results show the proposed LNA exhibits a peak gain of 17 dB, NF of 3.5-5.5 dB from 1 to 11 GHz and an IIP3 of -2.8 dBm at 6 GHz. It consumes 9 mW from a 1.2-V supply and occupies a very compact die area of 0.061 mm ² .

The effort to confine the electromagnetic field by silicon passive metadevices has made the design of an on-chip wideband sub-terahertz (sub-THz) I/O redriver feasible, paving a new way toward energy-efficient and crosstalk-immune ON–OFF keying (OOK) communications. Two metadevices, namely spoof surface plasmon polaritons (SPPs) metawaveguide and split-ring resonator (SRR), are exploited to build the sub-THz low-crosstalk silicon channel and high-ON–OFF-ratio modulator, respectively. A sub-THz signal source combining the merit of spoof SPPs and SRR is introduced. A 140-GHz dual-channel redriver composed of these metadevices is fully integrated in a 65-nm CMOS technology. The redriver realizes both 2 ⁷ –1 and 2 ³¹ –1 13.5 Gb/s/lane for dual-channel OOK modulation. The measured energy efficiency is 2.6 pJ/bit/lane and the bit error rate (BER) is ≤10 ⁻¹² , demonstrating a crosstalk-immune sub-THz I/O system. The power consumption is 35.1 mW/lane and the active area of the redriver is 0.23 mm ² .

In an effort toward high-speed and low-power I/O data link in the future exascale data server, this paper presents a signal source and a modulator in the D-band. The split-ring resonator (SRR) structures are used to boost both the signal power and the extinction ratio (ER). The modulator manifests itself as a compact SRR whose magnetic resonance frequency can be modulated by high-speed data. Such a magnetic metamaterial achieves a significant reduction of radiation loss with high ER by stacking two auxiliary SRR unit cells with interleaved placement. The high-Q tank for oscillation is realized by a stacked SRR decorated with slow-wave transmission line (T-line) for electric field confinement. A four-way power-combined fundamental 80-GHz coupled-oscillator network is magnetically synchronized by the slow-wave T-line, which is frequency doubled to 160 GHz. Fabricated in the 65-nm CMOS process, the measured results show that: 1) the modulator achieves 3-dB insertion loss at the on-state with 43-dB isolation at the off-state, leading to a 40-dB ER at 125 GHz within an area of only 40 μm x 67 μm and 2) the signal source achieves 6.3% frequency tuning range (FTR) with 3.7-mW peak output power at 160 GHz within 0.053-mm² active area. It has a measured phase noise of -105 dBc/Hz at 10-MHz offset, 5.5% dc-to-RF power efficiency, 70.1-mW/mm² power density, FOM of -171 dBc/Hz, and FOMT of -172.7 dBc/Hz.

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs _rms at 40.96 GHz and 122 fs _rms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW.