AlGaN/GaN-Si based MIS-HEMTs are considered as the popular candidates for application in the 5G communication system due to their competitive characteristics and low cost. Ohmic contact, as an important fabrication process, significantly affects the performance of the device. In this study, the ohmic contact process, including the SiN passivation layer etching, surface treatment, and barrier layer etching, was studied in detail in order to effectively optimize the device performance. It is observed that the sample with the SiN passivation layer etched by the magnetic neutral loop discharge (NLD) resulted in a lower contact resistance as compared to the reaction ion etching (RIE). The sample surface treated with the O plasma and pickled in the HCl:H ₂ O = 1:10 liquid could effectively remove the pollutants and oxides from the surface, thus, correspondingly presenting a lower ohmic contact resistance as compared to the N2 plasma. Meanwhile, an optimum etching depth was developed with the ICP process for 6 min with an etching speed of 1.6 nm/min. A contact resistance of 0.76 Ω · mm and square resistance of 274.63 ohm/sq were observed under the above-mentioned optimized ohmic contact process. The AlGaN/GaN-Si MIS-HEMT with gate length of 0.5 μm, gate-source space of 1 μm, gate-drain space of 2.5 μm, and gate width of 100 μm was fabricated using the optimized process. A saturation current density of 794.30 mA/mm and the maximum transconductance of 16.86 mS were observed. The findings in this study provide the experimental basis for the manufacturing of AlGaN/GaN-Si based MIS-HEMTs for RF applications.

An Sm-doped SnS₂/ZnS sensor shows excellent gas-sensing performance towards triethylamine at room temperature.

Gallium oxide (Ga₂O₃) devices have shown remarkable potential for high-voltage, high-power, and low-loss power applications. However, thermal management of packaging for Ga₂O₃ devices becomes challenging due to the significant self-heating effect. In this paper, an advanced double-sided cooling flip-chip packaging structure for Ga₂O₃ devices was proposed and the overall packaging of Ga₂O₃ chips was researched by simulation in detail. The advanced double-sided cooling flip-chip packaging structure was formed by adding a layer of diamond material on top of the device based on the single-sided flip-chip structure. With a power density of 3.2 W/mm, it was observed that the maximum temperature of the Ga₂O₃ chip with the advanced double-sided cooling flip-chip packaging structure was 103 °C. Compared with traditional wire bonding packaging and single-sided cooling flip-chip packaging, the maximum temperature was reduced by about 12 °C and 7 °C, respectively. When the maximum temperature of the chip was controlled at 200 °C, the Ga₂O₃ chip with double-sided cooling packaging could reach a power density of 6.8 W/mm. Finally, by equipping the top of the package with additional water-cooling equipment, the maximum temperature was reduced to 186 °C. These findings highlight the effectiveness of the proposed flip-chip design with double-sided cooling in enhancing the heat dissipation capability of Ga₂O₃ chips, suggesting promising prospects for this advanced packaging structure.

High-k/n-InAlAs MOS capacitors are popular for the isolated gate of InAs/AlSb and InAlAs/InGaAs high-electron mobility transistors. In this study, a new kind of high-k/n-InAlAs MOS-capacitor with a HfO₂–Al₂O₃ laminated dielectric was successfully fabricated using an optimized process. Compared with the traditional HfO₂/n-InAlAs MOS capacitor, the new device has a larger equivalent oxide thickness. Two devices, with a HfO₂ (8 nm)–Al₂O₃ (4 nm) laminated dielectric and a HfO₂ (4 nm)–Al₂O₃ (8 nm) laminated dielectric, respectively, were studied in comparison to analyze the effect of the thickness ratios of HfO₂ and Al₂O₃ on the performance of the devices. It was found that the device with a HfO₂ (4 nm)–Al₂O₃ (8 nm) laminated dielectric showed a lower effective density of oxide charges, and an evidently higher conduction band offset, making its leakage current achieve a significantly low value below 10⁻⁷ A/cm² under a bias voltage from −3 to 2 V. It was demonstrated that the HfO₂–Al₂O₃ laminated dielectric with a HfO₂ thickness of 4 nm and an Al₂O₃ thickness of 8 nm improves the performance of the high-k dielectric on InAlAs, which is advantageous for further applications.

A true random number generator (TRNG) based on a W/Ta ₂ O ₅ /Ag memristor was developed, which achieved image encryption of MNIST handwritten digits. This method effectively disrupts the pixel correlation of the original image.

With the continuous development of solar cells, the perovskite solar cells (PSCs), whose hole transport layer plays a vital part in collection of photogenerated carriers, have been studied by many researchers. Interface transport layers are important for efficiency and stability enhancement. In this paper, we demonstrated that lithium (Li) and cobalt (Co) codoped in the novel inorganic hole transport layer named NiO_x, which were deposited onto ITO substrates via solution methods at room temperature, can greatly enhance performance based on inverted structures of planar heterojunction PSCs. Compared to the pristine NiO_x films, doping a certain amount of Li and Co can increase optical transparency, work function, electrical conductivity and hole mobility of NiO_x film. Furthermore, experimental results certified that coating CH₃NH₃PbI_xCl_3−x perovskite films on Li and Co- NiO_x electrode interlayer film can improve chemical stability and absorbing ability of sunlight than the pristine NiO_x. Consequently, the power conversion efficiency (PCE) of PSCs has a great improvement from 14.1% to 18.7% when codoped with 10% Li and 5% Co in NiO_x. Moreover, the short-circuit current density (Jsc) was increased from 20.09 mA/cm² to 21.7 mA/cm² and the fill factor (FF) was enhanced from 0.70 to 0.75 for the PSCs. The experiment results demonstrated that the Li and Co codoped NiO_x can be a effective dopant to improve the performance of the PSCs.