Nabeel Ahmad

Mr. Nabeel Ahmad


Research Focus & Metrics

Academic Career Length

9Years (2018-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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30 November 2018 in Sensors
Verified
Journal Article
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BRBehnam Samadpoor Rikan
Behnam Samadpoor Rikan
SKSang-Yun Kim
Sang-Yun Kim
NANabeel Ahmad
Nabeel Ahmad
HAHamed Abbasizadeh
Hamed Abbasizadeh
MRMuhammad Riaz Ur Rehman
Muhammad Riaz Ur Rehman
Kang-Yoon LeeKang-Yoon Lee
Kang-Yoon Lee
This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.

23 March 2018 in Energies
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Journal Article
Open access
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YPYoung Jun Park
Young Jun Park
ZKZaffar Hayat Nawaz Khan
Zaffar Hayat Nawaz Khan
SOSeong Jin Oh
Seong Jin Oh
BJByeong Gi Jang
Byeong Gi Jang
NANabeel Ahmad
Nabeel Ahmad
Kang-Yoon LeeKang-Yoon Lee
Kang-Yoon Lee
In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.