This paper presents a reconfigurable wide input power range radio frequency (RF) energy harvester (EH) with alliance for wireless power (A4WP) wireless power receiver (WPR). A reconfigurable RF-DC converter for RF EH and maximum power point tracking algorithm are proposed to maintain high efficiency over a wide input power range -20 to +20 dBm. The A4WP WPR is designed and merged with the EH to receive power higher than +20 dBm. In order to improve the power conversion efficiency (PCE), the delay between the ac input voltage and current is compensated by the proposed open-loop delay compensation method. The chip is implemented in 0.18 μm bipolar-CMOS-double-diffused metal-oxide-semiconductor process. The die area of the chip is 4.3 mm × 3.2 mm, including the pads. The proposed EH with WPR achieves a measured peak PCE of 48.19% with respect to the input power of 0 dBm at 900 MHz. It also has a peak PCE of 82.14% with respect to the input power of 30 dBm in an A4WP mode operation at 6.78 MHz.

In this paper, a new two-stage class-AB operational trans-conductance amplifier (OTA) is proposed. Using active loads in the first stage and improved recycling structure (IRS), the effective trans-conductance of the first stage is increased. Nonlinear current mirrors boost the current of the second stage in the slewing mode, leading to the increase of the slew rate (SR). Exploiting the multi-path scheme and increasing the effective trans-conductance cause the OTA DC-gain to be enhanced. The proposed OTA has been fabricated using 1P6M 180-nm CMOS technology under 1.8 V supply voltage. The OTA exhibits 98 dB DC-gain and 21 MHz unity-gain bandwidth (UGBW) with a 100 pF capacitive load, consuming 3 mW from 1.8V supply voltage.

This article describes a multilevel hybrid plug-and-play dc–dc converter capable of converting a Li-ion battery input voltage range of 2.7–4.5 V to a system-on-chip voltage range of 0.6–1.3 V with an output spur as low as −53.5 dBm, a switching frequency variation of 0.13%, and peak efficiency of 88.6% at a corresponding power density of 0.061 W/mm ² . The converter, designed in 65-nm CMOS, uses a small 470-nH inductor and is stable with a multilayer ceramic output capacitor with only a 2-m $\Omega$ series resistance. A fully on-chip adaptive constant-on-time controller is employed, enabling a minimum efficiency of 70% for load currents as low as 30 mA with a response time of 3 $\mu$ s from a rapid 1-A load current step, without any need for external power supplies or control circuits.

In this paper, a low-power reconfigurable ambient Radio Frequency to Direct Current power (RF–DC) converter using an internal threshold voltage cancellation (IVC) scheme with an auxiliary transistors block is presented. A maximum power point tracking (MPPT) algorithm is implemented in order to maintain the high efficiency by automatically selecting the number of stages. The proposed reconfigurable converter efficiently converts the RF signals to DC voltage by dynamically controlling the threshold voltage of the forward and reversed-biased transistors in the primary rectification body. During positive half-cycle, the proposed RF–DC converter reduces the voltage drop across the forward-biased transistors, which results in increased harvested power and output DC voltage. During negative half cycle, the proposed rectifier minimizes the reverse leakage current and prevents the loss of energy stored in the prior stages. A five-stage internal threshold compensated power converter is designed in 0.18 µm Complementary Metal-Oxide-Semiconductor (CMOS) technology with an active die area of 360 µm × 160 µm, while the Maximum Power Point Tracking (MPPT) occupies an active die area of 730 µm × 280 µm. The proposed scheme obtains maximum post-simulated power conversion efficiency (PCE) of 39.3% when input power level is −15 dBm and produces an output voltage of 3.3 V for a load of 1 MΩ and at a frequency of 900 MHz. The proposed scheme achieves a voltage sensitivity of 1V at a remarkably low input power of −21 dBm for a 1 MΩ load.

A fully on-chip, low-power and small area CMOS Relaxation Oscillator (ROSC) with voltage integral feedback structure and a new Bandgap Reference voltage (BGR) for accurate oscillation frequency independent of the PVT and comparator's delay variations is presented. The designed circuit uses a new bandgap reference to generate the reference voltage required by relaxation oscillator which allow variations due to voltage and temperature to be compensated. Another merit of this oscillator is that the phase noise at low-offset frequency is suppressed by the voltage integral feedback circuit. The frequency of the relaxation oscillator is determined by the RC response time. Thus, the current and capacitance are controlled by temperature and process compensation circuits to compensate for the frequency variation. The ROSC is implemented in a 0.18μm CMOS technology and its active area is 0.14mm ² . The target frequency is 25MHz and current consumption is 22μA, where V _DD is 1.8V. The oscillation frequency variation for V _DD ranges from 1.4 to 1.9V is 0.2% and for temperature ranges from -40 to 125°C is 0.18%.

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be −7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement.