This paper presents a broadband Doherty power amplifier (DPA) design with an octave bandwidth based on a new load network consisting of a quasi-lumped impedance transformer for the carrier amplifier, a multiple resonance circuit for the peaking amplifier, and a broadband post-matching network. The quasi-lumped impedance transformer and the multiple resonance circuit were designed based on accurate equivalent circuits for internal components inside the packaged transistor. Based on power bandwidth analysis, optimum susceptance provided by the multiple resonance circuit at the peaking amplifier, was obtained. The proposed broadband DPA was designed using 45 W gallium-nitride high electron mobility transistor for both carrier and peaking amplifiers. For continuous-wave signals in frequency range of 0.9 to 1.8 GHz, the implemented broadband DPA exhibited a drain efficiency of 54.2% to 73.4% at peak output power of 49.7 to 51.4 dBm and a drain efficiency of 41.7% to 58.0% at output back-off of 6 dB. For the down-link long-term evolution signal with a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, a drain efficiency of 41.3% to 57.4% and an adjacent channel leakage power ratio of -22.5 to -30.2 dBc at an average output power of 43.2 to 449 dBm were achieved at an octave bandwidth.

In this paper, a high efficiency dc-dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc-dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc-dc converter. Also, all digital type-III compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5-3 V to generate the output voltage of 1.2 V. The total active area is 500 μm × 300 μm. The measured peak efficiency of the DPWM dc-dc buck converter is 91.5% with a quiescent current consuming only 130 μA.

This paper presents a Doherty power amplifier (DPA) based on asymmetric cells using an even input power drive and an appropriate peak fundamental current ratio (FCR) between the peaking amplifier and the carrier amplifier. Using an appropriate output combiner and an even input power drive for the DPA, not only better load modulation but also enhanced power gain can be achieved. After providing an analysis for the fundamental currents, a design guide for the proposed DPA using the peak FCR is presented. For verification, conventional and proposed DPAs were designed using GaN-HEMTs for the 2.14-GHz band. Using a downlink long-term evolution signal having a peak-to-average power ratio of 6.5 dB, comparably better performances were achieved than the conventional DPAs, such as a high power-added efficiency of 55.7% and a power gain of as high as 16.6 dB, at an average output power level of 36.9 dBm.

This paper presents a reconfigurable radio frequency to direct current (RF-DC) converter operating at 902 MHz frequency designed to efficiently harvest RF signals and convert into useable DC voltages for RF energy harvesting applications. The proposed scheme employs a dual-path, a series (lowpower) path and a parallel (high-power) path, to maintain high power conversion efficiency (PCE) over wide input power range. The dual-path is composed of two identical rectifier blocks utilizing internal threshold voltage cancellation (IVC) technique to efficiently compensate the threshold voltage of the transistors used as rectifying devices. An adaptive control circuit (ACC) consisting of a comparator, an inverter and three switches is used in the proposed scheme. The ACC activates the series path or the parallel path to maximize the harvested power based on the input power range. The proposed scheme is designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) technology. The measurement results show that PCE of the proposed circuit is above 20% from -18 dBm to -5 dBm, maintaining 13-dB input power range with peak PCE of 33% at -8 dBm for 200 kΩ load resistance. The proposed circuit demonstrates -20.2 dBm sensitivity across 1 MΩ load resistance while producing 1 V output DC voltage.

This article presents a high-efficiency fast transient constant on -time (COT) control dc–dc buck converter for the Internet of Things applications. The current reused current sensor is proposed to enhance the loop stability and improve the power conversion efficiency at light load. Input current is sensed and added to the feedback voltage of the dc–dc converter to increase the sensed output ripple voltage. Fast transient dc-offset cancelation technique is introduced to achieve a fast transient recovery time and to cancel the output dc offset. This chip is fabricated with a 0.13- μ m CMOS process. A standard supply voltage of 7–15 V is applied to produce the output voltage of 5–5.33 V. The total die area is 2 mm × 1.5 mm. The settling time is 17 μ s. The transient recovery time from light to heavy load and from heavy load to light load are 3 μ s and 2.7 μ s, respectively, with a maximum dc offset of 3.5 mV. The overshoot voltage is 85 mV and the undershoot voltage is 72 mV. The peak efficiency of the proposed design is 95.56% at 0.5 A and efficiency at the light load of 10 mA is 84.60%.

The retroreflective method has been used as a radio—frequency (RF) beamforming method for massive antenna array, for wireless communication systems, radars, and microwave power transfer (MPT) systems. In particular, the retroreflective method is suitable for optimum beamforming for both near—and far—field zones. Each transmitter (Tx) and receiver (Rx) circuit in the Tx array has its own phase offset, which should be calibrated for optimum retroreflective operation. This paper presents a simple and effective phase offset calibration method for the retroreflective beamforming arrays using a one—by—one basis optimum phase searching method with a receiver at a reference point. To verify the proposed method for a massive retroreflective array, a 5.2 GHz short— and mid—range (~ 4 m) MPT system, including a Tx array based on 8x8 antennas and an Rx using 6 antennas (5 rectennas for power reception, and 1 additional for pilot transmission) for charging mobile handsets was implemented. Optimal retroreflective beamforming from the Tx array, which was calibrated using the proposed method, was experimentally verified for angles of within ±45° degrees for both xz— and yz—planes. The implemented Tx and Rx circuits achieved a received dc power of about 100 mW at a distance of 4 m.