In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to ~50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.

Gate grounded tunnel field-effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET integrated circuits. It has been reported that two current paths exist when the ggTFET is turned on under the ESD events. In this work, the double current path phenomenon in ggTFETs is further investigated using TCAD simulation. It is found that the upper path is a hole current path, while the lower path mainly consists of electrons, and the grounded gate is a major factor that influences the double current path phenomenon. The heat and lattice temperature distributions in ggTFETs are also discussed.

Two novel 3×VDD-tolerant electrostatic discharge (ESD) protection circuits using only low-voltage devices without extra power consumption are proposed for 0.18- μm 1.8-V and 90-nm 1.2-V CMOS processes, respectively. Stacked-capacitor technique and bias circuit are adopted in the two designs. The proposed ESD detection circuits can generate 36- and 38-mA currents to trigger the ESD clamp device under the ESD event. Under normal operating conditions, all the devices are free from the gate-oxide reliability threat. The leakage currents of the 0.18- μm and 90-nm circuits are 0.9 and 200 nA under 3×VDD, respectively. The simulation results show that both the circuits can be successfully used for 3×VDD-tolerant I/O buffers.

An important development trend of ON-chip power clamp circuits is that they should be able to deal with more types of power rail overstress events, such as electrostatic discharges (ESDs) and surges. Generally, this requires that the clamp circuit can be fully turned on for the whole duration of the overstress events. In this work, a new MOSFET-based power clamp circuit for concurrent ESD and surge protection is proposed and successfully validated experimentally. An MOSFET controlled by a special bias circuit is inserted into a traditional voltage detector consisting of a diode string and a resistor, resulting in reductions in the leakage current and the trigger voltage. Moreover, the layout area of the proposed clamp circuit is smaller than the traditional RC- and diode-triggered clamp circuits. Practical application scenarios and performance comparisons with traditional circuits are also presented.