Reservoir computing is a powerful neural network–based computing paradigm for spatiotemporal signal processing. Recently, physical reservoirs have been explored based on various electronic devices with outstanding efficiency. However, the inflexible temporal dynamics of these reservoirs have posed fundamental restrictions in processing spatiotemporal signals with various timescales. Here, we fabricated thin-film transistors with controllable temporal dynamics, which can be easily tuned with electrical operation signals and showed excellent cycle-to-cycle uniformity. Based on this, we constructed a temporal adaptive reservoir capable of extracting temporal information of multiple timescales, thereby achieving improved accuracy in the human-activity-recognition task. Moreover, by leveraging the former computing output to modify the hyperparameters, we constructed a closed-loop architecture that equips the reservoir computing system with temporal self-adaptability according to the current input. The adaptability is demonstrated by accurate real-time recognition of objects moving at diverse speed levels. This work provides an approach for reservoir computing systems to achieve real-time processing of spatiotemporal signals with compound temporal characteristics.

The exponential growth of various complex images is putting tremendous pressure on storage systems. Here, we propose a memristor-based storage system with an integrated near-storage in-memory computing-based convolutional autoencoder compression network to boost the energy efficiency and speed of the image compression/retrieval and improve the storage density. We adopt the 4-bit memristor arrays to experimentally demonstrate the functions of the system. We propose a step-by-step quantization aware training scheme and an equivalent transformation for transpose convolution to improve the system performance. The system exhibits a high (>33 dB) peak signal-to-noise ratio in the compression and decompression of the ImageNet and Kodak24 datasets. Benchmark comparison results show that the 4-bit memristor-based storage system could reduce the latency and energy consumption by over 20×/5.6× and 180×/91×, respectively, compared with the server-grade central processing unit-based/the graphics processing unit-based processing system, and improve the storage density by more than 3 times.

Write disturb on half-selected (HS) cells is investigated through electrical measurements and large-scale array simulations. The experimental results collected from the individual devices under constant stress voltage and consecutive pulse operation are correlated with the HS cells in large-scale arrays based on a physics-based SPICE compact model. The impact of write/read disturb on the HS cells at different locations of the arrays is analyzed. Design guidelines for the optimized array size based on the experimental data and HSPICE simulations are presented: e.g., a 16 kb array can maintain its stored data pattern for 5×10 ⁶ pulses and will have 164 false bits among half-selected cells after write disturb.

To simplify the architecture of a neuromorphic system, it is extremely desirable to develop synaptic cells with the capacity of low operation power, high density integration, and well controlled synaptic behaviors. In this study, we develop a resistive switching device (ReRAM)-based synaptic cell, fabricated by the CMOS compatible nano-fabrication technology. The developed synaptic cell consists of one vertical gate-all-around Si nano-pillar transistor (1T) and one transition metal-oxide based resistive switching device (1R) stacked on top of the vertical transistor directly. Thanks to the vertical architecture and excellent controllability on the ON/OFF performance of the nano-pillar transistor, the 1T1R synaptic cell shows excellent characteristics such as extremely high-density integration ability with 4F² footprint, ultra-low operation current (<2 nA), fast switching speed (<10 ns), multilevel data storage and controllable synaptic switching, which are extremely desirable for simplifying the architecture of neuromorphic system.

In this article, we propose an efficient and robust spike-driven convolutional neural network (SCNN) based on the nor flash computing array (NFCA), which is mapped by the pretrained convolutional neural network with the same structure. The spike-driven system eliminates the additional analog-to-digital/digital-to-analog (AD/DA) conversion in the NFCA-based CNN. To study the performance of the hardware implementation, an NFCA-based SCNN for the recognition of the Mixed National Institute of Standards and Technology (MNIST) data set is simulated. Simulation results illustrate that the system achieves 97.94% accuracy with the computing speed of 1 x 10⁶ frame per second (fps). Compared with the typical mixed-signal NFCA-based CNN, the NFCA-based SCNN saves 97% area and 56% energy consumption. Moreover, the NFCA-based SCNN demonstrates great robustness to 30% image noise with less than 2% accuracy loss. The impact of random telegraph noise (RTN) is also greatly reduced in which less than 1% accuracy decrease can be achieved at the 32-nm technology node.