We report on demonstrating high performance lateral β-Ga₂O₃ metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-connected field plate (FP) on a thin (150 nm) and highly Si-doped (n = 1.5 × 10¹⁸ cm⁻³) β-Ga₂O₃ epitaxial channel layer grown by ozone molecular beam epitaxy (MBE) on Fe-doped semi-insulating (010) substrate. For a MOSFET with a gate-drain spacing (L_gd) of 25 μm, the three terminal off-state breakdown voltage (V_BR) tested in Fluorinert ambient reaches 2321 V. To the best of our knowledge, this is the first report of lateral β-Ga₂O₃ MOSFET with high V_BR of more than 2 kV and the highest V_BR attained among all the Ga₂O₃ MOSFETs. The breakdown voltages with different L_gd from 5–25 μm ranged from 518–2321V, with a linear trend of increasing breakdown voltage for larger spacing lateral MOSFETs. Combining with high electrical performances and excellent material properties, source-connected FP lateral β-Ga₂O₃ MOSFET implies its great potential for next generation high-voltage and high-power switching devices applications above 2 kV.

The ultra-wide bandgap (UWBG) energy (∼5.4 eV) of α-phase Ga2O3 offers the potential to achieve higher power switching performance and efficiency than today's power electronic devices. However, a major challenge to the development of the α-Ga2O3 power electronics is overheating, which can degrade the device performance and cause reliability issues. In this study, thermal characterization of an α-Ga2O3 MOSFET was performed using micro-Raman thermometry to understand the device self-heating behavior. The α-Ga2O3 MOSFET exhibits a channel temperature rise that is more than two times higher than that of a GaN high electron mobility transistor (HEMT). This is mainly because of the low thermal conductivity of α-Ga2O3 (11.9 ± 1.0 W/mK at room temperature), which was determined via laser-based pump-probe experiments. A hypothetical device structure was constructed via simulation that transfer-bonds the α-Ga2O3 epitaxial structure over a high thermal conductivity substrate. Modeling results suggest that the device thermal resistance can be reduced to a level comparable to or even better than those of today's GaN HEMTs using this strategy combined with thinning of the α-Ga2O3 buffer layer. The outcomes of this work suggest that device-level thermal management is essential to the successful deployment of UWBG α-Ga2O3 devices.

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate 0.12 μm × 100 µm T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the SiN_x. The SiN_x was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the SiN_x) with sample A (dry etching for the SiN_x), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.