Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

A high‐rate capability carbon‐encapsulated polyaniline (PANI) composite is fabricated by a novel electrodeposition method of polyaniline on a carbon nanotube (CNT) forest, grown on carbon paper. This is followed by coating of an amorphous carbon layer via hydrothermal carbonization (HTC) of glucose, forming a three‐layer structure. We demonstrate that a slow scan rate, voltage‐restricted electrodeposition process can be used to produce a uniform PANI coating on individual CNTs throughout the network. The CNT forest structure offers excellent electronic and structural connection for the PANI nanofiber network, while the coating of amorphous carbon reduces electrode resistance, promoting enhanced electrochemical performance and reinforced structural stability during charging and discharging. The as‐prepared CNT/PANI/HTC composite exhibited a high specific capacitance of 571 F g⁻¹ at 1 A g⁻¹, and 557 F g⁻¹ at 100 A g⁻¹,whilst demonstrating a record rate capability of 98% capacitance retention, when the current density is increased 100‐fold. This advanced rate performance indicates that a slow electrodeposition process produces an electrochemically stable three‐layer composite with enhanced diffusion kinetics. Hence, the method developed in this work establishes further control on the electrochemical deposition of energy storage materials, for high‐rate capability.

Pb‐Sn mixed perovskites are becoming increasingly popular as narrow‐bandgap (1.2–1.3 eV) light absorbers in single‐junction perovskite solar cells (PSCs) and as bottom cells for all‐perovskite tandem solar cells, for high‐efficiency, low‐cost, lightweight, roll‐to‐roll printable photovoltaic (PV) applications. From the first report of planar Pb:Sn mixed PSCs in 2014, the power conversion efficiencies (PCE) have increased from 10% to 21% by the end of 2020 with an exponential growth in research conducted in this field. Despite much effort, the performance and stability of Pb‐Sn mixed PSCs are still limited, which constrains their long‐term use in all‐perovskite tandem devices. This review highlights the avenues explored in improving different aspects of Pb‐Sn mixed PSCs and provides a comprehensive discussion of the interdependent factors affecting the device performance. This includes compositional engineering of the perovskite crystal, absorber layer fabrication and crystallization methods, bandgap tuning, Sn⁴⁺ reduction, and surface passivation of the absorber layer, as well as the selection of interlayers and electrodes of the final PSC.

Thin insulating layers are used to modulate a depletion region at the source of a thin‐film transistor. Bottom contact, staggered‐electrode indium gallium zinc oxide transistors with a 3 nm Al₂O₃ layer between the semiconductor and Ni source/drain contacts, show behaviors typical of source‐gated transistors (SGTs): low saturation voltage (V_{D_SAT} ≈ 3 V), change in V_{D_SAT} with a gate voltage of only 0.12 V V⁻¹, and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry: the saturated current changes only 0.15× for 2–50 µm channels and 2× for 9‐45 µm source‐gate overlaps. A higher than expected (5×) increase in drain current for a 30 K change in temperature, similar to Schottky‐contact SGTs, underlines a more complex device operation than previously theorized. Optimization for increasing intrinsic gain and reducing temperature effects is discussed. These devices complete the portfolio of contact‐controlled transistors, comprising devices with Schottky contacts, bulk barrier, or heterojunctions, and now, tunneling insulating layers. The findings should also apply to nanowire transistors, leading to new low‐power, robust design approaches as large‐scale fabrication techniques with sub‐nanometer control mature.

We report the need for careful selection of anti-solvents for Sn-based perovskite solar cells fabricated through the commonly used anti-solvent method, compared to their Pb-based counterparts. This, in combination with the film processing conditions used, enables the complete removal of unwanted Sn⁴⁺ dopants, through engineering the anti-solvent method for Sn-based perovskites. Using a Cs_0.05(FA_0.83MA_0.17)_0.95Pb_0.5Sn_0.5I₃ perovskite, charge carrier mobilities of 32 ± 3 cm² V⁻¹ s⁻¹ (the highest reported for such systems through the optical-pump terahertz probe technique) together with ∼28 mA cm⁻² short circuit current densities are achieved. A champion efficiency of 11.6% was obtained for solvent extraction using toluene (an 80% enhancement in efficiency compared to the other anti-solvents) which is further improved to 12.04% following optimised anti-solvent wash and thermal treatment. Our work highlights the importance of anti-solvents in managing defects for high efficiency low bandgap perovskite materials and develops the potential for all-perovskite tandem solar cells.