In this paper, the effect of common-mode voltage generated in the three-level quasi-switched boost T-type inverter is minimized by applying the proposed space-vector modulation technique, which uses only medium vectors and zero vector to synthesize the reference vector. The switching sequence is selected smoothly for inserting the shoot-through state for the inverter branch. The shoot-through vector is added within the zero vector in order to not affect the active vectors as well as the output voltage. In addition, the shoot-through control signal of active switches of the impedance network is generated to ensure that its phase is shifted 90 degrees compared to shoot through the signal of the inverter leg, which provides an improvement in reducing the inductor current ripple and enhancing the voltage gain. The effectiveness of the proposed method is verified through simulation and experimental results. In addition, the superiority of the proposed scheme is demonstrated by comparing it to the conventional pulse-width modulation technique.

In this paper, a new pulse width modulation (PWM) scheme using an offset function to reduce switching loss in the five-level H-bridge T-type inverter (5L-HBT²I) is proposed. The proposed modulation technique is implemented with a third harmonic offset voltage function. A new control voltage, that is adding the offset voltage into the initial control, is shifted to the top or bottom position of the carrier, simultaneously—where the absolute value of its load current is high or medium in comparison to other phase load currents. Due to reducing the intersection between a control voltage and the carriers, the number of switch commutations of the inverter is reduced. As a result of reducing the number of commutation count with a high current at the non-switching position, the switching losses of the inverter are decreased. Analysis and comparison of switching losses on the two-level and three-level inverters, which are components of 5L-HBT²I are presented. The power loss analysis on the 5L-HBT²I is performed. The proposed technique implements the switching loss reduction strategy based on setting the operation of the two-level inverter in six-step mode. PSIM software is used to clarify the proposed technique. The simulation results show that the total switching losses of the proposed technique in 5L-HBT2I reduce in comparison to the conventional sine PWM technique. A prototype is built to validate the proposed scheme. Simulation and experimental results match the analysis.

This paper proposes the non-isolated DC-DC converter with high boost ratios and efficiency. We suggest boosting methods including voltage multiplier cells or coupled inductors. However, both techniques have a limited constant voltage multiplier coefficient according to the fixed configuration. Therefore, in the proposed method, we change the multiplier factor (as the number of activity levels) and combine it with the turn of the appropriate duty cycle; these factors are considered at the same time in order to increase the energy conversion efficiency and expand the control area of the duty cycle. A mathematical analysis of the losses of the components in operation modes shows that the boost ratio and efficiency are functions of the number of activity levels and duty cycle. Therefore, this paper proposes an algorithm for tracking the activity levels and duty cycle in order to obtain the maximum efficiency. The simulations produced with the Powersim-PSIM software, and the experiments with load capacities of 250 W, 500 W and 1000 W, boosting the ratio by more than ten times, were conducted in order to clarify the capabilities of the proposed configuration.

In this paper, a controlled diode bridge clamped three-level inverter topology based on quasi-switched boost network (CDBC-qSBI) is presented. The proposed inverter not only inherits the advantages of traditional qSBIs but also it has the unique features: use of less number of high power passive reactive elements in the intermediate network as well as isolated DC power supply which increases the system size. On the other hand, it is able to provide both buck and boost voltages and produces a required three-phase three-level AC output voltage in a single-stage conversion. The proposed topology has continuous input current and controlled diode bridge clamped three-level inverter to avoid the reverse recovery problem. Circuit analysis and simulation results of the proposed three-level CDBC-qSBI are presented. A 600-W prototype based on a TMS320F28335 digital signal processor is built to verify the operating principle of the three-level CDBC-qSBI.

The article introduces a non-isolated positive output buck-boost converter that is capable of operating across a wide duty cycle range. The converter exhibits low nonlinearity in its voltage gain relative to D, thereby enhancing its capability to regulate output voltage or effectively regulate current over a broad duty cycle spectrum. A comparison of the performance of the proposed converter with existing converters is presented, with a particular consideration of the DC gain, voltage and current stresses on switches and diodes, and inductor currents. The comprehensive calculations include ideal and practical voltage gains, current assessments, stress analysis on components, parameter design, efficiency, and brief discussions on the discontinuous conduction mode and boundary conditions. The converter exhibits peak efficiencies of approximately 98.98% in boost mode and 99.16% in buck mode, which represent a notable advancement in power electronics. It is noteworthy that the converter displays minimal current and voltage overshoot in buck mode with a conversion ratio below 3. The overshoot relative to the normalized current is less than 1, reaching a minimum of 0.21, while the voltage overshoot is as low as 0.51. This contributes to superior buck mode efficiency. A laboratory model was developed with great care to validate the converter's experimental outcomes and theoretical evaluations. This provides reassurance about the reliability of the research.

This paper presents a carrier modulation technique to control the three-phase, two-level quasi switched boost inverter. This PWM algorithm uses three carrier waves, the first of which is for the inverter while the others are for the booster. The boost factor depends on the short circuit interval on the DC/DC booster and the inverter. When the short circuit interval on the DC boost is twice that on the inverter, the modulation index can be enlarged. The new algorithm is analyzed, calculated, simulated, and tested. The analysis and calculation results show that the proposed technique can reduce the voltage on the DC link capacitor compared to a conventional approach. It can reach 22.16% when the ratio of the DC source voltage to the effective reference voltage is 0.5. The modulation index can extend to 29% under these conditions and the current ripple in the boost inductor can be reduced by 4.8%. The simulation and experimental results also show similarities, thereby confirming the analysis and calculation.