Object detection and classification is an essential task of computer vision. A very efficient algorithm for detection and classification is YOLO (You Look Only Once). We consider hardware architectures to run YOLO in real-time on embedded platforms. Designing a new dedicated accelerator for each new version of YOLO is not feasible given the fast delivery of new versions. This work's primary goal is to design a configurable and scalable core for creating specific object detection and classification systems based on YOLO, targeting embedded platforms. The core accelerates the execution of all the algorithm steps, including pre-processing, model inference and post-processing. It considers a fixed-point format, linearised activation functions, batch-normalisation, folding, and a hardware structure that exploits most of the available parallelism in CNN processing. The proposed core is configured for real-time execution of YOLOv3-Tiny and YOLOv4-Tiny, integrated into a RISC-V-based system-on-chip architecture and prototyped in an UltraScale XCKU040 FPGA (Field Programmable Gate Array). The solution achieves a performance of 32 and 31 frames per second for YOLOv3-Tiny and YOLOv4-Tiny, respectively, with a 16-bit fixed-point format. Compared to previous proposals, it improves the frame rate at a higher performance efficiency. The performance, area efficiency and configurability of the proposed core enable the fast development of real-time YOLO-based object detectors on embedded systems.

Deep learning is now present in a wide range of services and applications, replacing and complementing other machine learning algorithms. Performing training and inference of deep neural networks using the cloud computing model is not viable for applications where low latency is required. Furthermore, the rapid proliferation of the Internet of Things will generate a large volume of data to be processed, which will soon overload the capacity of cloud servers. One solution is to process the data at the edge devices themselves, in order to alleviate cloud server workloads and improve latency. However, edge devices are less powerful than cloud servers, and many are subject to energy constraints. Hence, new resource and energy-oriented deep learning models are required, as well as new computing platforms. This paper reviews the main research directions for edge computing deep learning algorithms.

This paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the C/I₁ MHz, and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node (0.13 μm), occupying a silicon area smaller than 0.7 mm². The receiver achieves a sensitivity level of -92 dBm while consuming 1.41 mA from a 1.2-V supply.