This paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the C/I₁ MHz, and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node (0.13 μm), occupying a silicon area smaller than 0.7 mm². The receiver achieves a sensitivity level of -92 dBm while consuming 1.41 mA from a 1.2-V supply.

Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuits for fifth-generation (5G) communications systems. However, the proper analysis of their design tradeoffs that allow for a realistic topology comparison is impractical. The many conflicting specifications that must be carefully balanced make the problem intractable. In this paper, the 148-dimensional performance spaces of three 28-GHz LNAs are fully explored for a 65-nm CMOS technology node, using an enhanced electronic design automation tool. One- and two-step many-objective optimizations provide up to 1024 different LNAs for each of the considered topologies, enabling a thorough assessment of their performance tradeoffs. The first optimizes all the design parameters at once. In contrast, the latter optimizes the spiral inductors in a first step. Then, in a second step, it optimizes the remaining parameters. The resulting designs provide new insight on the tradeoffs between gain, noise figure, power, and circuit's footprint for current 5G specifications. Process, voltage, and temperature corners impact the LNAs' performance severely. Still, the optimization shows that proper sizing of these topologies compete with the most-recent mmWave LNAs and can play a role in the challenging 28-GHz band.

Current-mode class-D (CMCD) power amplifiers (PAs) may not achieve a switching efficiency as good as class-E PAs, but they require fewer inductances and deliver almost five times more power for the same load and supply voltage when compared with the ideal push-pull class-E PA. Furthermore, CMCD PAs can easily use bondwires as the only circuit inductors, a precious feature that Internet-of-Things (IoT) wireless interfaces can exploit. For this reason, we analyze the voltage and current waveforms in CMCD PAs without assuming infinite value feeding inductors (i.e., without choke inductors). It is shown that the current stress on the switching device is significantly higher than in the conventional topology, especially in bondwire-based designs where relatively small feeding inductances are presented. Finally, we propose a design procedure for a given feeding inductance that maximizes energy efficiency while delivering a compact-size solution. A 2.4-GHz PA capable of delivering 19.8 dBm to a 100-Ω differential load with a power-added-efficiency (PAE) of 58% is presented. Three-dimensional electromagnetic (3-D EM) simulations combined with postlayout simulations were used to evaluate the PA performance in a quad-flat nonlead (QFN)-type package. The circuit is designed in a 0.13-μm process and only occupies a silicon area of 0.025 mm ² .

This paper presents a detailed analysis of thermal coupling and self-heating effects in highly integrated wireless transmitters. A MIMO transmitter prototype consisting of two closely integrated power amplifiers was built and modelled through microwave and thermal characterizations. The thermal behavior was extracted using FEM software and modelled with an equivalent RC network. The PA model was obtained experimentally using a pulsed setup. An RF-thermal simulator was developed and used with the models to predict joint thermal and electrical behavior. Measurements with modulated communication signals were done and compared with the simulator to demonstrate its feasibility for analysis of thermal effects in highly integrated transmitter applications.

This letter presents an all-digital low-IF Gaussian Frequency-Shift Keying (GFSK) demodulator. The demodulator is based on a quadrature FM discriminator followed by a bit decision unit. An intermediate-frequency (IF) input signal of 1MHz is used, the same value of the data rate, hence allowing a low-power receiver implementation. By monitoring the SNR of the input packet during the preamble, poor SNR packets are discarded to avoid energy waste with non-decodable packets. The circuit occupies a silicon area of 0.048 mm ² in a 130nm process. Measurements show a state-of-the-art current consumption of about 170 μA from a single 1.2V supply. The proposed demodulator requires an SNR of 14.4 dB for a BER of 0.1%.

This paper presents a fully integrated single-ended power amplifier for ultra-low-power applications. The single-ended configuration is possible due to a choke-inductor less output network capable of rejecting the 2nd-harmonic emission. A switching duty-ratio lower than 50% avoids the impedance transformation output network traditionally required for proper class-E operation. At 2.45 GHz, the PA (including the driver) delivers 1.4 dBm to a 50 Ω load and achieves an overall efficiency of 51% while complying with the spurious emission regulation. The prototype was fabricated in 0.13 μm CMOS.