In this letter, a compact SiC power module featuring low stray inductance and balanced thermal resistance is proposed. To make full utilization of SiC devices in high-frequency and high-power-density applications, the laminated busbar and double-sided cooling heatsinks are directly packed as parts of SiC power module. To balance the mechanical and thermal stress on the chips, a press-pack-like package technology is adopted. The electrical and thermal experiments of the prototype are evaluated to validate the design of low inductance and balanced thermal distribution.

In this paper, the impact of a double-sided press-pack insulated-gate-bipolar-transistor (PP IGBT) cooling structure on its thermal impedance distribution is studied and explored. A matrix thermal impedance network model is built by considering the multi-chip thermal coupling effect for the collector side of the PP IGBT. Moreover, a verification has been made by comparing the proposed matrix thermal network model and the conventional lumped RC network model provided by the manufacturer. It is concluded that the collector side has lower thermal resistance and dissipates about 88% of the heat generated by the IGBT chips inside the module. Then, a modular-multilevel-converter high-voltage-direct-current (MMC-HVDC)-based type test setup composed of the press-pack IGBT stacks is established and the junction temperature is calculated with the proposed thermal model and verified by temperature measurements.

In this paper, the distributed-press-pack (DPP) packaging technology is developed to achieve balanced thermal stress on the chips. Under the current lumped-press-pack (LPP) style, the mechanical stress distribution on the chips, which is inherently uneven and coupled with thermal stress distribution, can be described with elastic half-space theoretical model. By decentralizing the lumped pressing load and positioning the loads evenly, a matrix of clamping array is formulated and the mechanical stress distribution is compared under different clamping ways. Then, a 3*3 clamping method that meets the trade-off between balanced stress distribution and the packaging cost is chosen. Meanwhile, the busbar and heatsinks are integrated to improve the power density of the power module. Finally, a DPP prototype is implemented. By varying the pressure around the chips and heating them, the thermal distribution between parallel chips inside the prototype is compared and the effect of proposed elastic half-space theory based DPP packaging technology on the thermal stress balance is verified.