A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors ( $\Delta V_{\mathrm {GS}}$ ) operating in weak inversion mode, while the second one ( $V_{\text {NL}}$ ) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard $0.18 \mathrm {\mu m}$ CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5–15 ppm/°C in the temperature range of −10 °C to 110 °C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 °C to 150 °C. The supply current consumption is $150 ~\mu \text{A}$ , and the chip area is $0.56\times0.8$ mm2. The measured peak noise at the output is $1.42 ~\mu \text{V}/\sqrt {\text {Hz}} $ @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.

An integrated lock-in amplifier (LIA) with automatic phase tuning and second-order harmonic frequency extraction is presented in this paper. The automatic phase alignment loop implemented in the proposed single-channel LIA can directly align the phases of an input signal with a reference signal. Furthermore, the proposed LIA system also includes an enhanced signal detection method in which the 2^nd harmonics of the carrier frequency (ω_ref) is applied. As opposed to conventional LIA, this method reduces flicker noise and input offset effects that limit the signal-to-noise ratio (SNR). In terms of signal power detection, the proposed single-channel LIA architecture does not require phase synchronization between input and reference signals. The circuit is designed for a reference frequency of 100 Hz, suitable for biomedical applications. The LIA is Implemented using 0.18-μm CMOS technology with a single power supply voltage of 1.8 V. The system consumes 360 μW at an operating frequency of 100 Hz and presents a high input sensitivity dynamic range for a detection bandwidth of 50 Hz and a FOM of 116 dB.

A low power, high sensitivity, super-regenerative (SR) receiver for wireless body area networks (WBANs) is proposed in this brief. To enable high sensitivity while maintaining low power consumption, a two-step periodically quenching controller with automatic negative transconductance (-G _m ) controller is designed for tuning the biasing current of the superregenerative oscillator (SRO) at twice the data rate of the input signal. To reduce the power consumption without compromising the loop gain, a novel cross-coupled SRO architecture using gm-boosting, adaptive bulk biasing, and dynamic threshold control techniques is presented. The proposed super-regenerative receiver with a center frequency of 2.4-GHz is implemented in 180-nm CMOS technology. Simulation results show that this receiver achieves a BER of 2 × 10 ^-3 at SNR = 12 dB and sensitivity of -87 dBm at 3.3 Mb/s while consuming 398 μW.

This paper presents a new technique for minimizing spurs in charge-pump phase-locked loop (PLL) using pulse injection (PI) technique. The proposed background calibration uses pulse injection in parallel with the normal operation of the PLL during its unlocked phase to extract the charge pump current mismatch error. The mismatch extraction is implemented using an error integrator and a successive approximation register (SAR) controller configured in a negative feedback to perform background calibration during the normal operation of the PLL. A windowing clock is used to extract only the error caused by the injected pulses and maintain the control voltage dc level outside of the window. Upon completion of calibration, the injection pulses are stopped and the PLL continues its operation in the lock state with minimized spur. The proposed technique successfully achieves fast calibration without interrupting the normal operation of the PLL. The simulation results show good improvements of spur reduction stemmed from the charge-pump.

This paper presents an analog-assisted hybrid low-dropout regulator (LDO) with a wide load current range and fast transient response. The proposed design is composed of digital and analog loops of which the transient response is dictated by the digital portion. A fast approximation algorithm leveraging charge distribution reduces settling time significantly compared to linear and SAR approaches. A wide load range droop detector further improves transient response with negligible power overhead. The analog assisted circuits continuously provide current in response to the load current change without disturbing the loop dynamic. Implemented in a TSMC 180-nm standard CMOS technology, the LDO supports a 430 mA maximum load and ensures loop stability without external capacitors. It achieves a 480 mV undershoot at 430 mA with 100 ns edge time, $49~\mu $ A quiescent current, and settling times of 225 ns and 260 ns for undershoot and overshoot at $C_{L}=0$ pF when a 10-MHz clock is used. Measurement shows that activating the droop detector reduces undershoot by 54%.

A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.