A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors ( $\Delta V_{\mathrm {GS}}$ ) operating in weak inversion mode, while the second one ( $V_{\text {NL}}$ ) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard $0.18 \mathrm {\mu m}$ CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5–15 ppm/°C in the temperature range of −10 °C to 110 °C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 °C to 150 °C. The supply current consumption is $150 ~\mu \text{A}$ , and the chip area is $0.56\times0.8$ mm2. The measured peak noise at the output is $1.42 ~\mu \text{V}/\sqrt {\text {Hz}} $ @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.

People's increasing demand for high-quality network services has prompted the continuous attention and development of network traffic classification (NTC). In recent years, deep flow inspection (DFI) is considered to be the most effective and promising method to solve the NTC. However, DFI still cannot effectively address the problem of changes in flow characteristics of complex packet flows and the discovery of new traffic categories. In this paper, we propose a metric learning based deep learning solution with feature compressor, named deep flow embedding (DFE). The feature compressor is used to compress the feature information transmitted layer by layer in DL backbone while maintaining the computational accuracy, so that the backbone can remove as much noise, redundancy, and other irrelevant information from the input data as possible, and achieve more robust feature extraction of network traffic flow. The deep learning (DL) backbone generates an embedding vector for each network packet flow. Then the embedding vector is compared with the vector template preset for each traffic type in the template library to determine the category of the packet flow. Experimental results verify that our method is more effective than the traditional DFI methods in overcoming the problems of flow characteristics variation and new category discovery.

An integrated lock-in amplifier (LIA) with automatic phase tuning and second-order harmonic frequency extraction is presented in this paper. The automatic phase alignment loop implemented in the proposed single-channel LIA can directly align the phases of an input signal with a reference signal. Furthermore, the proposed LIA system also includes an enhanced signal detection method in which the 2^nd harmonics of the carrier frequency (ω_ref) is applied. As opposed to conventional LIA, this method reduces flicker noise and input offset effects that limit the signal-to-noise ratio (SNR). In terms of signal power detection, the proposed single-channel LIA architecture does not require phase synchronization between input and reference signals. The circuit is designed for a reference frequency of 100 Hz, suitable for biomedical applications. The LIA is Implemented using 0.18-μm CMOS technology with a single power supply voltage of 1.8 V. The system consumes 360 μW at an operating frequency of 100 Hz and presents a high input sensitivity dynamic range for a detection bandwidth of 50 Hz and a FOM of 116 dB.

This paper presents a new technique for minimizing spurs in charge-pump phase-locked loop (PLL) using pulse injection (PI) technique. The proposed background calibration uses pulse injection in parallel with the normal operation of the PLL during its unlocked phase to extract the charge pump current mismatch error. The mismatch extraction is implemented using an error integrator and a successive approximation register (SAR) controller configured in a negative feedback to perform background calibration during the normal operation of the PLL. A windowing clock is used to extract only the error caused by the injected pulses and maintain the control voltage dc level outside of the window. Upon completion of calibration, the injection pulses are stopped and the PLL continues its operation in the lock state with minimized spur. The proposed technique successfully achieves fast calibration without interrupting the normal operation of the PLL. The simulation results show good improvements of spur reduction stemmed from the charge-pump.

An intermittent frequency synthesizer for fast duty-cycled receivers is presented in this paper. Different from state-of-art techniques which try to eliminate the initial phase error that degrades the intermittent frequency detection, a new frequency detector is proposed to maintain an accurate frequency detection regardless of the initial phase error. Moreover, an averaged fraction division scheme (AFDS) is integrated in the synthesizer to improve the frequency resolution. The frequency synthesizer is implemented and verified by using discrete devices and an FPGA. The measurement results show that the frequency detector provides a frequency detection accuracy of 0.88%, and the synthesizer achieves a frequency resolution of 0.625 MHz when controlled by a duty-cycled signal with a 6-μs period and a 2-μs time duration. The frequency synthesizer can perform an intermittent frequency hopping from 160MHz to 140MHz while requiring a period of 430 μs without disturbing the VCO’s oscillation.

A process-voltage-temperature (PVT)-robust, low power, low noise, and high sensitivity, super-regenerative (SR) receiver is proposed in this paper. To enable high sensitivity and robust-PVT operation, a fast locking phase-locked-loop (PLL) with initial random phase error reduction is proposed to continuously adjust the center frequency deviations of the SR oscillator (SRO) without interrupting the input data stream. Additionally, a concurrent quenching waveform (CQW) technique is devised to improve the SRO sensitivity and its noise performance. The proposed SRO architecture is controlled by two separate biasing branches to extend the sensitivity accumulation (SA) phase and reduce its noise during the SR phase, compared to the conventional optimal quenching waveform (OQW). The proposed SR receiver is implemented at 2.46 GHz center frequency in 180 nm SMIC CMOS technology and achieves better sensitivity, power consumption, noise performance, and PVT immunity compared with existent SR receiver architectures.