A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor (MOSFET) with heavily-doped n+ source and drain junctions, nearly intrinsic n- channel, 500-nm gate length (LG), and 50-nm poly-Si body thickness (Tbody). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by grain boundaries (GBs) capable of charge trapping not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of 3.2 μA/μm and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.

Memristor devices are considered to have the potential to implement unsupervised learning, especially spike timing-dependent plasticity (STDP), in the field of neuromorphic hardware research. In this study, a neuromorphic hardware system for multilayer unsupervised learning was designed, and unsupervised learning was performed with a memristor neural network. We showed that the nonlinear characteristic memristor neural network can be trained by unsupervised learning only with the correlation between inputs and outputs. Moreover, a method to train nonlinear memristor devices in a supervised manner, named guide training, was devised. Memristor devices have a nonlinear characteristic, which makes implementing machine learning algorithms, such as backpropagation, difficult. The guide-training algorithm devised in this paper updates the synaptic weights by only using the correlations between inputs and outputs, and therefore, neither complex mathematical formulas nor computations are required during the training. Thus, it is considered appropriate to train a nonlinear memristor neural network. All training and inference simulations were performed using the designed neuromorphic hardware system. With the system and memristor neural network, the image classification was successfully done using both the Hebbian unsupervised training and guide supervised training methods.

In this paper, a physical unclonable function (PUF), a type of hardware security device, is proposed to overcome the limitations of existing security schemes. A $32\times 32$ crossbar array using TiO _x /Al ₂ O _3- based memristors was fabricated, and electrical characteristics including its set voltage distribution were analyzed. The memristor switching characteristics model is described in a simplified space-charge-limited current (SCLC) regime. Based on this I-V model, selected bit-line current PUFs (SBC-PUFs) were designed with $32\times 32$ , $64\times 64$ , and $128\times 128$ crossbar arrays. The entropy source of these PUFs is the set voltage deviation in the fabricated memristors. Due to these characteristics, the SBC-PUF can exploit the broad resistance distribution near the switching region, including the internal resistance distributions of the high resistance state (HRS) and low resistance state (LRS). The SBC-PUF performance was evaluated for randomness/uniformity, correctness/reliability, and uniqueness by calculating the Hamming weight and intra/inter Hamming distance of challenge-response pairs (CRPs). The designed structure demonstrates high-security performance due to the high value of these indicators and the large number of CRPs. Furthermore, the devised PUF has a higher prediction error rate than arbiter PUF in machine learning attacks. This study verified that the SBC-PUF using the memristor of the crossbar array structure is safe enough to be used for hardware security.

Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell’s data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell’s state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area.

Spin-torque oscillator (STO) is a promising new technology for the future RF oscillators, which is based on the spin-transfer torque (STT) effect in magnetic multilayered nanostructure. It is expected to provide a larger tunability, smaller size, lower power consumption, and higher level of integration than the semiconductor-based oscillators. In our previous work, a circuit-level model of the giant magnetoresistance (GMR) STO was proposed. In this paper, we present a physics-based circuit-level model of the magnetic tunnel junction (MTJ)-based STO. MTJ-STO model includes the effect of perpendicular torque that has been ignored in the GMR-STO model. The variations of three major characteristics, generation frequency, mean oscillation power, and generation linewidth of an MTJ-STO with respect to the amount of perpendicular torque, are investigated, and the results are applied to our model. The operation of the model was verified by HSPICE simulation, and the results show an excellent agreement with the experimental data. The results also prove that a full circuit-level simulation with MJT-STO devices can be made with our proposed model.