In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

In this work, a ZnO-based resistive switching memory device is characterized by using simplified electrical conduction models. The conventional bipolar resistive switching and complementary resistive switching modes are accomplished by tuning the bias voltage condition. The material and chemical information of the device stack including the interfacial layer of TiON is well confirmed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) analysis. The device exhibits uniform gradual bipolar resistive switching (BRS) with good endurance and self-compliance characteristics. Moreover, complementary resistive switching (CRS) is achieved by applying the compliance current at negative bias and increasing the voltage at positive bias. The synaptic behaviors such as long-term potentiation and long-term depression are emulated by applying consecutive pulse input to the device. The CRS mode has a higher array size in the cross-point array structure than the BRS mode due to more nonlinear I–V characteristics in the CRS mode. However, we reveal that the BRS mode shows a better pattern recognition rate than the CRS mode due to more uniform conductance update.

In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear ${C} - {V}$ characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.

Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the nand flash array structure. We demonstrate a Hf $_\text{0.5}$ Zr $_\text{0.5}$ O $_\text{2}$ (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high on/off ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D nand architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D nand architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip ( ex-situ ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.

In this paper, a physical unclonable function (PUF), a type of hardware security device, is proposed to overcome the limitations of existing security schemes. A $32\times 32$ crossbar array using TiO _x /Al ₂ O _3- based memristors was fabricated, and electrical characteristics including its set voltage distribution were analyzed. The memristor switching characteristics model is described in a simplified space-charge-limited current (SCLC) regime. Based on this I-V model, selected bit-line current PUFs (SBC-PUFs) were designed with $32\times 32$ , $64\times 64$ , and $128\times 128$ crossbar arrays. The entropy source of these PUFs is the set voltage deviation in the fabricated memristors. Due to these characteristics, the SBC-PUF can exploit the broad resistance distribution near the switching region, including the internal resistance distributions of the high resistance state (HRS) and low resistance state (LRS). The SBC-PUF performance was evaluated for randomness/uniformity, correctness/reliability, and uniqueness by calculating the Hamming weight and intra/inter Hamming distance of challenge-response pairs (CRPs). The designed structure demonstrates high-security performance due to the high value of these indicators and the large number of CRPs. Furthermore, the devised PUF has a higher prediction error rate than arbiter PUF in machine learning attacks. This study verified that the SBC-PUF using the memristor of the crossbar array structure is safe enough to be used for hardware security.