This paper proposes a loop-free auto-calibration technique for self-balancing of flying capacitors in a three-level DC–DC buck converter. The proposed converter utilizes a dual- path power stage with balancing switches that adaptively short flying capacitors at de-energizing phases. Thus, the dual-path three-level converter ensures that flying capacitor voltages are self-balanced at half the input voltage without using additional feedback calibration loops, leading to robust operation and competitive efficiencies. The prototype was fabricated in 0.13-μm CMOS BCD process and adopted two flying capacitors of 4.7 μF each and an inductor of 10 μH with a DC resistance of 128 mA. When an 8 V input was converted to a 3 V output voltage with a load current of 400 mA, the measured efficiency was 88.6% at 800 kHz switching, while flying capacitors are automatically balanced.

This paper proposes a new boost converter topology called dual-path step-up DC-DC converter (DPUC). Unlike the conventional boost converter (CBC), the DPUC has a hybrid structure using one inductor and one flying capacitor to make dual current delivery paths. This allows continuous current delivering to the output, reducing both the DC level of the inductor current and the output voltage ripple. Therefore, the DPUC has higher efficiency and smaller output voltage ripple than those of CBC. In addition, the feedforward characteristic of the flying capacitor can alleviate the effect of RHP-zero that degrades the transient response. Even with the inductor DCR of 200mΩ, the DPUC achieves a high efficiency of 95.2% and a small ripple of up to 15mV.

This article proposes a series- LC resonant current mode receiver (RCM R _X ) for wirelessly powered battery chargers. With a series- LC scheme, the RCM R _X can operate at higher resonant voltages than transistor breakdown voltages, enabling robust near-field wireless power transfer. In the series- LC RCM R _X , a dual automated maximum efficiency control (AMEC) and a passive zero-current detector (ZCD) adaptively adjust operation states, ensuring nonresidual energy in the R _X LC tank at the end of the charging mode. Moreover, the passive ZCD operation algorithm increases the power delivered to the load or battery by minimizing the idle period between charging and resonant modes. The 180-nm standard CMOS chip, which used only 1.8-V transistors, can operate with 6.84× higher resonant voltage up to 12.32 V than the transistor breakdown voltage, 1.8 V, while receiving an input power up to 169 mW, enabling a wide input range over variable coil distances. The proposed system achieves the measured power conversion efficiency up to 84.9% at the input power of 16.8 mW.

This paper proposes a bandgap reference (BGR)-recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the bandgap reference circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5-μm 5-V CMOS devices. The PSR was measured to be -102 to -80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C $_OUT$ ≥ 1 μF. The proposed LDO consumes only 50 μA at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit (FoM) of 11 ps in the transient response.

The energy harvesting interface circuit is proposed for wind-driven triboelectric nanogenerator (WD-TENG). To extract power from the WD-TENG maximally and deliver power to the output (battery) efficiently, a rectifier-reusing bias-flip (RRBF) technique and a multiphase reconfigurable switched-capacitor converter (MRSCC) are developed. In the RRBF, the low-side switches of the rectifier are reused as switches for bias-flip without additional components. The MRSCC delivers power to the battery efficiently by reducing switching loss including overlap loss. Furthermore, the MRSCC maintains a rectified voltage ( V _RECT ) as high as a breakdown voltage ( V_BR ) of a switch by adaptive conversion control and multiphase operation to extract maximized power from the WD-TENG in a given process, even if the battery voltage is varied from 2.7 to 4.2 V. Owing to the proposed techniques, the maximum extracted power to the output is 238 μW and peak power delivering efficiency of the MRSCC is 79.3%. The chip was fabricated in 0.18 μm BCD process.