A novel heterojunction symmetric U-shaped gate tunnel FET (SUTFET) is proposed and investigated by Silvaco Atlas simulation. The U-shaped gate in the SUTFET can enlarge the area of the tunneling junction and facilitate the implementation of a smaller device area. Benefit from the line band-to-band tunneling process and symmetric structure design, bidirectional current flows (I _ON = 13.5 μA/μm, I _OFF = 3.1 pA/μm at V _GS = V _DS = 0.5 V) with the steep-switching feature of subthreshold slope (SS = 15.2 mV/decade at V _GS = 0.05 V and average SS = 37.2 mV/decade from 0 V <; VGS <; 0.05 V) are implemented. The effects of doping concentration and geometric dimensions on the device performance are investigated in order to create the SUTFET design guideline. The considerable good performance of the SUTFET makes it very attractive for ultralow-power applications.

In this letter, a novel U-shaped channel tunneling FET (UTFET) with heterogeneous gate dielectric (HG-UTFET) is designed to reduce the Miller capacitance (C _M ) and to improve the performance of TFET digital circuits. Because the HG-UTFET and UTFET have the same gate dielectric near the source region, these two devices nearly have the same on-state current. But due to the smaller gate-to-drain capacitance (C _gd ) caused by the low-k gate dielectric near the drain region, the HG-UTFET has smaller C _M compared with UTFET, which will enhance the switching performance of digital circuits. The simulation results reveal that the overshoot/undershoot and rising/falling delay of the output signal in the HG-UTFET inverter are reduced a lot compared with the UTFET inverter. Results show that the C _M and falling delay of the HG-UTFET inverter are ~45.6% and ~30.7% less than that of the UTFET inverter, respectively. Therefore, by the application of HG-UTFET, the switching performance of inverter can be enhanced a lot.

As an important supplementary material to graphene in the optoelectronics field, molybdenum disulfide (MoS₂) has attracted attention from researchers due to its good light absorption capacity and adjustable bandgap. In this paper, MoS₂ layers are respectively grown on SiO₂/Si and sapphire substrates by atmospheric pressure chemical vapor deposition (APCVD). Atomic force microscopy, optical microscopy, and Raman and photoluminescence spectroscopy are used to probe the optical properties of MoS₂ on SiO₂/Si and sapphire substrates systematically. The peak shift between the characteristic A_1g and E¹_2g peaks increases, and the I peak of the PL spectrum on the SiO₂/Si substrate redshifts slightly when the layer numbers were increased, which can help in obtaining the layer number and peak position of MoS₂. Moreover, the difference from monolayer MoS₂ on the SiO₂/Si substrate is that the B peak of the PL spectrum has a blueshift of 56 meV and the characteristic E¹_2g peak of the Raman spectrum has no blueshift. The 1- and 2-layer MoS₂ on a sapphire substrate had a higher PL peak intensity than that of the SiO₂/Si substrate. When the laser wavelength is transformed from 532 to 633 nm, the position of I exciton peak has a blueshift of 16 meV, and the PL intensity of monolayer MoS₂ on the SiO₂/Si substrate increases. The optical properties of MoS₂ can be obtained, which is helpful for the fabrication of optoelectronic devices.

In this paper, a dual metallic material gate heterostructure junctionless tunnel field-effect transistor (DMMG-HJLTFET) is proposed and investigated. We use the Si/SiGe heterostructure at the source/channel interface to improve the band to band tunneling (BTBT) rate, and introduce a sandwich stack (GaAs/Si/GaAs) at the drain region to suppress the OFF-state current and ambiplolar current. Simultaneously, to further decrease ambipolar current, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2), and tunnel gate (M3) with workfunctions Φ_M1, Φ_M2 and Φ_M3, respectively, where Φ_M1 = Φ_M3 < Φ_M2. Simulation results indicate that DMMG-HJLTFET provides superior performance in terms of logic and analog/RF as compared with other possible combinations, the ON-state current of the DMMG-HJLTFET increases up to $9.04\times 10^{-6}$ A/μm, and the maximum g_m (which determine the analog performance of devices) of DMMG-HJLTFET is $1.11\times 10^{-5}$ S/μm at 1.0V drain-to-source voltage (Vds). Meanwhile, RF performance of devices depends on the cut-off frequency (f_T) and gain bandwidth (GBW), and DMMG-HJLTFET could achieve a maximum f_T of 5.84 GHz, and a maximum GBW of 0.39 GHz, respectively.

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si_0.3Ge_0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO₂, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si_0.3Ge_0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 10¹², which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications.

A high performance doping-less tunneling field effect transistor with Ge/Si_0.6Ge_0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si_0.6Ge_0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits.