An embedded digital temperature sensor based on a single-ended probe is implemented in a 28 nm fully-depleted silicon-on-insulator (FD-SOI) process. The nMOS-only ring-oscillator probe uses single-point calibration based on body-bias tuning of its well for process compensation. Non-linearity compensation is implemented on-chip in custom digital logic, resulting in an area-efficient (225 μm2 per probe, 11482 μm2 for the full system) sensor while achieving -1.4∘C / +1.3∘C accuracy using 2.0 nJ/Sample and maintaining functionality over a 0.62V-1.2V range, making it suitable for temperature monitoring in digital systems-on-chip (SoCs).

The design of ultra-low-voltage microcontroller (MCU) systems with high energy-efficiency operations is a key concept to achieve fully autonomous energy-harvesting powered Internet-of-Things applications. In this paper, a system-on-chip (SoC) is presented, embedding an ARM® Cortex®-M0+ MCU, 2x4 KB SRAM, an ultra-low power frequency synthesizer, a custom power switch, and a power management unit enabling the active and sleep modes. The 28 nm fully depleted silicon-on-insulator (FD-SOI) technology has been used to fabricate the device. The whole system operates at a fixed voltage of 0.5 V, and can switch from active and sleep/deep sleep modes, adjusting its frequency from 16 to 8 MHz or 32 kHz in one cycle upon energy availability. Silicon measurements report an SoC's power consumption of 2.7 pJ/cycle at 16 MHz during active mode, and a total power consumption of 0.7 μW during deep sleep mode. By combining frequency and power modes switching with extra reverse body-biasing, the system power consumption is drastically reduced by $2x$ and $61x$ in, respectively, sleep and deep sleep modes.

The relentless pace of transistor miniaturization has enabled developers to continuously increase chip complexity since the beginning of the information age. However, as transistors get smaller and chips become larger, the cost of manufacturing ICs becomes increasingly prohibitive. As Moore’s Law is coming to an end, industry and academia have been exploring new paradigms to keep up with the ever-increasing demand for performance and functionality while dealing with the constraints of power consumption, area, and yield constraints. In this context, 3DICs are considered the future of the IC industry as they enable designers to fulfill both the “More Moore" and the “More than Moore" paradigm. A key feature of the 3DIC is that it can be manufactured by assembling multiple chiplets. Chiplets are single-purpose dies that must be assembled with other chiplets to form a complete system. Researchers and industry leaders believe that a chiplet market will form and that products with off-the-shelf chiplets will emerge. This scenario offers many economic opportunities. However, it also raises concerns regarding the security and trust (S&T) of chiplet-based designs. Malicious chiplets, Hardware trojans, and chiplet intellectual property theft are threats that must be addressed as the industry moves towards the “chiplet age". In this survey, we introduce the different types of 3DICs and their production chain.We then define the threats that threaten the different steps of the 3DIC manufacturing process. Finally, we present and discuss the state of the art in hardware S&T techniques for chiplet-based 3DICs.

In this article, we present the effects of voltage scaling and forward body biasing (FBB) on single-event effect sensitivity of a 28-nm ultra-thin body and box (UTBB) fully depleted silicon on insulator (FD-SOI) technology. Heavy-ion irradiation was performed for single-event upset (SEU) and single-event transient (SET) sensitivity assessment on characterization test chips under three supply voltages, with and without back-gate voltage application. Measurements show a steady SEU sensitivity for any supply voltage across the two FBB configurations, whereas SET sensitivity is diminished under FBB. SPICE and TCAD mixed-mode simulations were run to assess the contribution of electrical factors as well as charge extraction mechanisms. While drive strength is increased under FBB, the bipolar amplification plays an important role in sensitivity at low linear energy transfers (LETs).

In this paper we present a study of Single-Event Transients (SET) through an integrated test vehicle. This block was designed and manufactured within two test-chips in 28nm and 22nm FDSOI advanced technologies. Radiation testing was performed on those test-chips in order to characterize SETs. The results are cross-coupled with Monte-Carlo simulations and discussed.