An embedded digital temperature sensor based on a single-ended probe is implemented in a 28 nm fully-depleted silicon-on-insulator (FD-SOI) process. The nMOS-only ring-oscillator probe uses single-point calibration based on body-bias tuning of its well for process compensation. Non-linearity compensation is implemented on-chip in custom digital logic, resulting in an area-efficient (225 μm2 per probe, 11482 μm2 for the full system) sensor while achieving -1.4∘C / +1.3∘C accuracy using 2.0 nJ/Sample and maintaining functionality over a 0.62V-1.2V range, making it suitable for temperature monitoring in digital systems-on-chip (SoCs).

The design of ultra-low-voltage microcontroller (MCU) systems with high energy-efficiency operations is a key concept to achieve fully autonomous energy-harvesting powered Internet-of-Things applications. In this paper, a system-on-chip (SoC) is presented, embedding an ARM® Cortex®-M0+ MCU, 2x4 KB SRAM, an ultra-low power frequency synthesizer, a custom power switch, and a power management unit enabling the active and sleep modes. The 28 nm fully depleted silicon-on-insulator (FD-SOI) technology has been used to fabricate the device. The whole system operates at a fixed voltage of 0.5 V, and can switch from active and sleep/deep sleep modes, adjusting its frequency from 16 to 8 MHz or 32 kHz in one cycle upon energy availability. Silicon measurements report an SoC's power consumption of 2.7 pJ/cycle at 16 MHz during active mode, and a total power consumption of 0.7 μW during deep sleep mode. By combining frequency and power modes switching with extra reverse body-biasing, the system power consumption is drastically reduced by $2x$ and $61x$ in, respectively, sleep and deep sleep modes.

ITER is of key importance in the European fusion roadmap as it aims to prove the scientific and technological feasibility of fusion as a future energy source. The EUROfusion consortium of labs within Europe is contributing to the preparation of ITER scientific exploitation and operation and aspires to exploit ITER outcomes in view of DEMO. The paper provides an overview of the major progress obtained recently, carried out in the frame of the new (initiated in 2021) EUROfusion work-package called ‘Preparation of ITER Operation’ (PrIO). The overview paper is directly supported by the eleven EUROfusion PrIO contributions given at the 29th Fusion Energy Conference (16–21 October 2023) London, UK [www.iaea.org/events/fec2023]. The paper covers the following topics: (i) development and validation of tools in support to ITER operation (plasma breakdown/burn-through with evolving plasma volume, new infra-red synthetic diagnostic for off-line analysis and wall monitoring using Artificial Intelligence techniques, synthetic diagnostics development, development and exploitation of multi-machine databases); (ii) R&D for the radio-frequency ITER neutral beam sources leading to long duration of negative deuterium/hydrogen ions current extraction at ELISE and participation in the neutral beam test facility with progress on the ITER source SPIDER, and, the commissioning of the 1 MV high voltage accelerator (MITICA) with lessons learned for ITER; (iii) validation of neutronic tools for ITER nuclear operation following the second JET deuterium–tritium experimental campaigns carried out in 2021 and in 2023 (neutron streaming and shutdown dose rate calculation, water activation and activated corrosion products with advanced fluid dynamic simulation; irradiation of several materials under 14.1 MeV neutron flux etc).

This review paper aims to provide a survey of modeling and simulation of single-event effects (SEEs) in digital electronics at device, circuit and system levels. It primarily focuses on the specific multi-scale, multi-physics, multi-domain nature of SEEs and on the main underlying physical mechanisms that lead to the occurrence of single events in digital devices and circuits. This review addresses the different ways to model and simulate both in space and time this complex sequence of mechanisms from the particle-material interaction up to the electrical response of a given electronics device, circuit, or system. It highlights the specific features of each methodology, and discusses simulation requirements, code or model inputs and expected outputs.

We address accurate computation of on-orbit upset rates in advanced technologies, with a focus on FD-SOI at the 28 nm node. Heavy-ion measurements performed on FD-SOI SRAM bit-cells give experimental evidence of the technology's intrinsic robustness in space environments; this extreme reduction of sensitive volume dimensions deeply affects the assumptions pertaining to the radiation response models used to predict upset rates. The generic “Integral Rectangular ParallelePiped” (IRPP) model, although requiring careful setting of its parameters, provides us with first-order estimates of the error rate. We then present a custom FD-SOI response model within our Monte-Carlo simulation chain, enabling comparison with IRPP and further analyses.

A new computational model for charge transport based on parallelized random-walk drift-diffusion is proposed. This approach models the radiation-induced charge carriers as charge packets in a 3-D structure and the transport modeling are based on simple physical equations without any fitting parameter. This model has been dynamically coupled with a SPICE circuit simulator to take into account temporal variations of the electric fields in the charge collection process. Thus, the circuit electrical response modulates the charge collection efficiency. Three simulation cases have been explored and compared with TCAD simulations or radiation experiments in 65 nm technology to validate the accuracy of the proposed approach. These simulations demonstrate the capability of the proposed model to accurately estimate the soft error rate of complex structures, such as flip-flops over a large range of ionizing particle linear energy transfer. The proposed simulation methodology is also able to take into account charge-sharing phenomenon, and this point is highlighted by a specific investigation on the considered flip-flop.