The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (V_t) tuning of the metal gate in contact with HfO₂/SiO₂/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

The temperature dependence of magnetoresistance and switching characterization based on spin transfer torque (STT) effect of perpendicular magnetic tunnel junctions (p-MTJs) with MgO/CoFeB/W/CoFeB/MgO double-interface free layer was studied. The tunneling magnetoresistance (TMR) ratio increases from 95% to 176% for both 84 and 64 nm-diameter p-MTJs, upon decreasing the temperature from 400 to 20 K. This change of TMR is dominated by a steady increase in the resistance of antiparallel state while the parallel state conductance remains almost constant. Switching behavior at various temperatures is investigated for pulse voltage-dependent STT measurements; resistance versus voltage loops for both the switching directions become more symmetric with decreasing temperature. Furthermore, low-temperature measurements of magnetic properties suggest that the effect of stray field for STT becomes weaker as the temperature decreases, which suggests the p-MTJs design for cryogenic memories.

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-x Ge x growth (0.35 ≤ × ≤ 0.40) with boron concentration of 1–3 × 1020 cm−3 was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.

An architecture for three-dimensional integration of dynamic random-access memory that enables higher memory density is presented as a new solution to the bottleneck currently faced in artificial intelligence deployment. The basis of this architecture is a vertical dual-gate two-transistors-zero-capacitor memory cell which yields a small feature size and reliable read operation, and naturally scalable to large-scale arrays. However, three-dimensional integration of the dynamic random-access memory faces highly-limiting challenges related to lateral misalignment and thermal cycling as a result of separate stacking processes. To solve the issues of cell misalignment and thermal cycling, a single step process is used to stack the dual-gate In-Ga-Zn-O transistors simultaneously. By optimizing the contact metallization and its interface through an in-situ ozone oxidation method, the vertical dual-gate transistor exhibits a high on-state current and small subthreshold slope as well as high thermal stability and device variation. Furthermore, a four-bit multi-bit operation is demonstrated with an ultra-scaled 4F² two-transistors-zero-capacitor dynamic random-access memory to further increase the storage density. The approach presented here provides a promising alternative to high-density three-dimensional dynamic random-access memory integration as a means for more efficient near memory computing for artificial intelligence systems.

An overview is given on the possibilities of using generation‐recombination (GR) noise as a tool for defect spectroscopy in semiconductor materials and devices. The method is illustrated by n‐channel MOSFETs fabricated on silicon‐on‐insulator (SOI) substrates with an ultra‐thin buried oxide (UTBOX). As will be shown, the use of fully depleted (FD) UTBOX devices offers some unique opportunities and challenges. In the first instance, one can apply the standard GR noise spectroscopy in function of the temperature to derive the relevant deep‐level parameters like the activation energy, the capture cross section and the concentration. In addition, some new type of spectroscopy can be applied to defects in the silicon film by exploiting the front‐ and/or back‐gate bias dependence of the Lorentzian noise parameters. Finally, it is shown that for small geometry transistors the GR noise is generated by one or only a few centres. This becomes obvious in the time domain, where the channel current exhibits random telegraph signal (RTS) fluctuations. The up and down time constants and the relative RTS amplitude can be used to derive the GR centre parameters and, moreover, its spatial location, when combined with numerical device simulations.