Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

Multilevel-cell (MLC) phase change memory (PCM) usually evaluated in the program method, delay or write energy while the endurance characteristic has not been focused on. In this paper, we exploit a staircase-up program and verify method in the current-driven 4 Mb PCM chip to achieve MLC storage. The direct results of the change in the R – I characteristic and resistance distribution during the cycles are displayed. According to the measurement, the PCM device shows four separable resistance levels after 10 ⁶ operation cycles with a decreasing resistance of full-crystalline state. And the resistance drift and read disturb which affect the cell reliability also are briefly tested. The MLC device shows a good performance where four resistance levels can be separated well after 1000 s and the read endurance under 0.3 V is retained up to 10 ⁹ cycles.

Phase change memory (PCM) device using a diode as selector exhibits a high level of integration based on 40 nm process, but it still has some reliability problems, such as read disturbance and writing performance. In this paper, we test and improve the read/write reliability of one diode and one resistor (1D1R) structure cell in array with cell size of 12 F ² (0.16 μ m × 0.12 μ m). The 1D1R device has good performance with ultra-high speed (20 ns) and low programming voltage (3.3 V). The cell programmed by current pulse has a better performance than that of voltage operation in amorphous state with respect to read disturb immunity. The ratio of reset/set resistance can be improved by choosing appropriate parameter of write operation. In addition, the endurance characteristics of the devices are investigated. The optimization in read/write operation guarantee that 1D1R device can satisfy the requirements for the high-speed and high-density applications.

The blade bottom electrode contact (BEC) can significantly reduce the programming current of the phase change memory (PCM) and achieve low power consumption compared with the typical T-shaped PCM cell. The method of controlling the electrode width by controlling the thickness of the deposited layer can make the size break through the limit of photolithography. This paper proves that the RESET programming current and power consumption of the PCM decrease linearly with the decrease of the blade BEC width, and builds a theoretical model to verify it by simulating the distribution internal temperature field. Based on the above research, the cell life of PCM with different electrode widths was tested, and it was proved that the endurance of PCM increased with the decrease of the width of the blade electrode, caused by the lower power consumption of the narrower electrode.

Subsequent set pulse in stair-case pulse, which is used to control the cooling process of phase change memory (PCM), is still not enough in-depth exploration. A detailed investigation that the effect of subsequent set pulse on the set resistance distribution is presented. The improper subsequent set pulse amplitude and duration cause the cooling process of phase change material to deviate from the crystallization requirements, which leads to poor set resistance distribution. The optimal cooling current (OCC) can generate a linear decrease of the temperature, it is necessary for optimum crystallization. The thermal simulation suggests that the optimal subsequent set pulse has a similar temperature evolution to OCC. Hence the optimal subsequent set pulse enables minimum resistance, and its amplitudes are from 400 to 80 μ A and each pulse duration is 50 ns.

In this paper, aiming at the consistency of driving current and the reliability of crosstalk current, we propose two methods to optimize the performance of the dual-trench epitaxial diode array for phase change memory (PCM), as well as the optimization calculation model. By inserting pickup and using the new bias scheme, we can improve the consistency of the diode arrays and reduce the impact of crosstalk current on the idle storage cell, respectively. The test results show that all the diodes in arrays, including 4F ² in 40 nm process node, can provide a driving current of more than 900 μ A at 2.7 V, after inserting pickups. With the new bias scheme, the maximum of the crosstalk ratio in the 12F ² diode array can be reduced to less than 2%, which is proved has no effect on the idle PCM cell. Moreover, the optimization model is the basis of design and fabrication to improve the performance of the diode access PCM chip.