Chiplet-based packaging technology integrates multiple heterogeneous dies with different functions and materials into a single system as a LEGO-based approach using advanced packaging technology. However, it also brings new challenges in the thermal design aspect and thermal crosstalk between chiplets. In this article, the thermal modeling of a chiplet-based packaging with a 2.5-D interposer was carried out. Two chiplets were mounted on the interposer side-by-side. A Cu lid was attached to the top surfaces of the chiplets and periphery of the interposer through the thermal interface material1 (TIM1) and adhesive, respectively. To further dissipate the heat from the top side, a heat sink was attached to the top surface of the lid through a layer of TIM2. The effects of the TIM type, bonding approach between chiplets and interposer, heat sink structure, thermal crosstalk, convective heat transfer coefficient above the lid, and thermal design power (TDP) were analyzed. The study results show that the bumpless interconnect is beneficial for the heat dissipation of the chiplet-based packaging. The staggered column fin can exhibit superior cooling performance. The short pitch would bring cooling challenges for fine-pitch multiple chiplets integration. The temperature is decreased rapidly first and then slowed down with the increase of convective heat transfer coefficient above the lid. Under 10 000 W/ $\text{m}^{2}\cdot \text{K}$ , the maximum TDP was about 250 W.

In this paper, we propose a spike-time based unsupervised learning method using spiking-timing dependent plasticity (STDP). A simplified linear STDP learning rule is proposed for the energy efficient weight updates. To reduce unnecessary computations for the input spike values, a stop mechanism of the forward pass is introduced in the forward pass. In addition, a hardware-friendly input quantization scheme is used to reduce the computational complexities in both the encoding phase and the forward pass. We construct a two-layer fully-connected spiking neuron network (SNN) based on the proposed method. Compared to general rate-based SNNs trained by STDP, the proposed method reduces the complexity of network architecture (an extra inhibitory layer is not needed) and the computations of synaptic weight updates. According to the fixed-point simulation with 9-bit synaptic weights, the proposed SNN with 6144 excitatory neurons achieves 96% of recognition accuracy on MNIST dataset without any supervision. An SNN processor that contains 384 excitatory neurons with on-chip learning capability is designed and implemented with 28 nm CMOS technology based on the proposed low complexity methods. The SNN processor achieves an accuracy of 93% on MNIST dataset. The implementation results show that the SNN processor achieves a throughput of 277.78k FPS with 0.50 $\mu$ J/inference energy consuming in inference mode, and a throughput of 211.77k FPS with 0.66 $\mu$ J/learning energy consuming in learning mode.

Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C.

Spiking Neural Networks (SNNs) is promising to enable low power and high performance edge computing hardware design and have recently attracted attentions of researchers. Compared to Artificial Neural Networks (ANNs), SNNs, which present more realistic brain-inspired computing models, are developed as an alternative to ANNs. However, the temporal primitive of SNNs causes irregular and repeated data accesses, leading to high latency and extra power consumption. In this work, we propose an efficient architecture for SNNs by exploiting event-based characteristics. A reconfigurable spiking neuron processing unit is proposed to support a variety of spike-layers. Furthermore, to reduce the cycles needed per frame, an efficient dataflow with fast-filtering mechanism is introduced to leverage the sparsity of discrete spikes. The results show that this design achieves 67.5 $\mu \text{J}$ /image prediction energy with a throughput of 2.2K FPS. The core size is 0.89 mm ² under 28-nm technology, with 90.98% computing hardware utilization and a competitive accuracy 97.10% on a driving dataset.

We present a CORDIC (Coordinate Rotation Digital Computer)-based method to compute the logarithm function with base 2 and validate this method by software simulation and hardware implementation. Technically, we overcome the limitation of traditional hyperbolic CORDIC and transform it based on the idea of generalized hyperbolic CORDIC so that it can be used to compute log ₂ x (x ε [1, 2)). The proposed method requires only simple shift-and-add operations and has a great tradeoff between precision (or speed) and area. In MATLAB, we provide different precisions corresponding to the iterations of the transformed CORDIC for user needs. Using a pipelined structure and setting the number of iterations to be 16 (the average relative error is 2.09×10 ^-6 ), we implement an example hardware circuit. Synthesized under the SMIC 65nm CMOS technology, the circuit has an area of 24100 μm ² and computation time of 11.1 ns, which can save 31.04% area and improve 6.92% computation speed averagely compared with existing methods.