This work presents a comprehensive study on a particular kind of conveyor called second-generation voltage conveyor (VCII). This building block is based on voltage conveying concept and is the dual of second generation current conveyor (CCII). It is shown that VCII is a very useful block in those configurations where CCII is limited, in terms of number of active blocks. The results of this study are helpful in choosing the best building block between CCII and VCII for each specific application. Finally, for the first time, the CMOS implementation of VCII is also presented. Simulation results with PSPICE using 0.35μm CMOS technology and supply voltage of ±1.65V are given to approve the theory.

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 μm CMOS technology parameters at a supply voltage of ±0.9 V are provided to support the presented theory.

In this paper, a new circuit topology to realize an electronically tunable grounded capacitor multiplier with extremely low power consumption and low supply voltage requirement is investigated. The proposed circuit uses an electronically tunable second generation voltage conveyor (VCII) and a single floating capacitor. Owing to the translinear principle, current gain of VCII is varied through a control current and, as a result, the value of simulated capacitor is also varied. Favorably the obtained gain is temperature insensitive. Both of the required supply voltage and control currents are very low because all transistors are biased in subthreshold region: therefore, electronic tunability is achieved while the power consumption is kept at very low value. In addition, the circuit realization is very simple since only twelve transistors are required. Simulation results, performed at schematic level in 0.18μm CMOS technology and supply voltage of ±0.3V, are presented. It is shown that a multiplication factor from 1 to 100 is possible while the power consumption varies from 10 nW to 67 nW.

A new low-voltage low-power class-AB second generation voltage conveyor (VCII) is presented. The proposed circuit is based on an improved class-AB flipped voltage follower (FVF) designed by adding a simple negative feedback loop to the conventional class-AB circuit. This modification ensures high current drive capability of at least 2mA for both falling and rising edges of input signal along with very low 2mΩ output impedance and high accuracy. Benefiting from the new class-AB FVF, the proposed VCII features a very simple implementation, extremely low impedance at Y and Z terminals (2mΩ), high impedance at X terminal (370kΩ) and high accuracy in current and voltage conveying (99% and 98% respectively). Moreover, it exhibits current drive capability 117.6 times larger than its bias current (17μA). The circuit occupies 381.5μm*197μm area. The application of the proposed VCII as a voltage integrator is also presented. Simulation results using PSpice and 0.35μm CMOS technology with ±1.65V supply voltage are provided to demonstrate the presented theory. A comparison with the literature is also provided.

In this paper, a novel approach to implement a stray insensitive CMOS interface for differential capacitive sensors is presented. The proposed circuit employs, for the first time, second-generation voltage conveyors (VCIIs) and produces an output voltage proportional to differential capacitor changes. Using VCIIs as active devices inherently allows the circuit to process the signal in the current domain, and hence, to benefit from its intrinsic advantages, such as high speed and simple implementation, while still being able to natively interface with voltage mode signal processing stages at necessity. The insensitiveness to the effects of parasitic capacitances is achieved through a simple feedback loop. In addition, the proposed circuit shows a very simple and switch-free structure (which can be used for both linear and hyperbolic sensors), improving its accuracy. The readout circuit was designed in a standard 0.35 μm CMOS technology under a supply voltage of ±1.65 V. Before the integrated circuit fabrication, to produce tangible proof of the effectiveness of the proposed architecture, a discrete version of the circuit was also prototyped using AD844 and LF411 to implement a discrete VCII. The achieved measurement results are in good agreement with theory and simulations, showing a constant sensitivity up to 412 mV/pF, a maximum linearity error of 1.9%FS, and acknowledging a good behavior with low baseline capacitive sensors (10 pF in the proposed measurements). A final table is also given to summarize the key specs of the proposed work comparing them to the available literature.