Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.

In the past year, fifth-generation (5G) wireless technology has seen dramatic growth, spurred on by the continuing demand for faster data communications with lower latency. At the same time, many researchers argue that 5G will be inadequate in a short time, given the explosive growth of machine connectivity, such as the Internet-of-Things (IoT). This has prompted many to question what comes after 5G. The obvious answer is sixth-generation (6G), however, the substance of 6G is still very much undefined, leaving much to the imagination in terms of real-world implementation. What is clear, however, is that the next generation will likely involve the use of terahertz frequency (0.1–10 THz) electromagnetic waves. Here, we review recent research in terahertz wireless communications and technology, focusing on three broad topic classes: the terahertz channel, terahertz devices, and space-based terahertz system considerations. In all of these, we describe the nature of the research, the specific challenges involved, and current research findings. We conclude by providing a brief perspective on the path forward.

A compact, low loss, wideband digital step attenuator (DSA) is presented. The proposed DSA utilizes amplitude/phase-compensated T-type attenuator cells, in which the locations of poles and zeros are manipulated for minimizing variations in attenuation and phase. In addition, the reduced T-type attenuator cells that eliminate series switch transistors are used to achieve low insertion loss (IL). These techniques provide wideband (dc-20 GHz) operation for the DSA, with significantly decreased attenuation/phase errors and reduced IL. The DSA was implemented in a 130-nm silicon-germanium (SiGe) BiCMOS platform. The full attenuator circuit has binary-coded 6-bit digital control inputs with a least significant bit of 0.5-dB attenuation. It has a root-mean-square (rms) attenuation error of 0.37 dB and an rms phase error of 4°, both at 20 GHz. The IL and the input 1-dB compression point at 10 GHz are 4 dB and 10 dBm, respectively. The active core layout area is 0.14 mm² 1.0 mm x 0.14 mm).

In this letter, it is proposed that g_m ²/I_D, which has been used as the figure of merit (FoM) of MOSFETs for analog amplifiers, can also be used as the RF MOSFET FoM for optimizing low-noise amplifier (LNA) performance. From a simple small-signal equivalent circuit, signal gain, noise figure, and power consumption equations are derived analytically and verified with the measurement results of the fabricated LNA. The proposed g_m ²/I_D predicts the optimal bias point for the maximum LNA performance.

In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect transistor (FET) with variations of active area specifications including number of vertically stacked channels, metal gate thickness, and channel width, is investigated using TCAD simulations. Our research suggests that varying these architecture parameters not only affect overall performance of sub-5-nm node GAA nanoplate FET such as on-current degradation and time-delay, but also greatly impact thermal reliability such as lattice temperature and thermal resistance, which are comprehensively analyzed using the Figure of Merit (FoM). Furthermore, thermal reliability of GAA nanoplate-FET is analyzed from perspective of Hot Carrier Injection (HCI) / Bias Temperature Instability (BTI) lifetime variation using maximum lattice temperature (TL,max) and metal gate thickness (TM).

This paper presents a true time delay (TTD)-based transmit/receive (T /R) chipset with 508 ps time delay and 31.5 dB amplitude control for large-scale wideband timed array. The proposed T /R chipset consists of a true time delay circuit, a switched T -type attenuator, and digital control circuits. To compensate the frequency dependent insertion loss characteristics of single-pole double-throw switches, artificial transmission line (ATL), passive-based attenuator, and wideband bi-directional active double-pole double-throw (DPDT) switches are included in the design. In addition, low-path filters (LPFs) with T -type attenuators are applied to the reference signal path to minimize amplitude variations during time delay control. The proposed T /R chipset demonstrates a record delay-range bandwidth product and a flat in-band characteristic of -3.6 dB with ±3.6 dB variation in both operations (transmit and receive) over 2-20 GHz.