A compact, low loss, wideband digital step attenuator (DSA) is presented. The proposed DSA utilizes amplitude/phase-compensated T-type attenuator cells, in which the locations of poles and zeros are manipulated for minimizing variations in attenuation and phase. In addition, the reduced T-type attenuator cells that eliminate series switch transistors are used to achieve low insertion loss (IL). These techniques provide wideband (dc-20 GHz) operation for the DSA, with significantly decreased attenuation/phase errors and reduced IL. The DSA was implemented in a 130-nm silicon-germanium (SiGe) BiCMOS platform. The full attenuator circuit has binary-coded 6-bit digital control inputs with a least significant bit of 0.5-dB attenuation. It has a root-mean-square (rms) attenuation error of 0.37 dB and an rms phase error of 4°, both at 20 GHz. The IL and the input 1-dB compression point at 10 GHz are 4 dB and 10 dBm, respectively. The active core layout area is 0.14 mm² 1.0 mm x 0.14 mm).

This letter presents new wideband single-pole double-throw (SPDT) RF switches utilizing SiGe heterojunction bipolar transistors (HBTs) for both series and shunt switches. SiGe HBT, when used as a series switch, exhibits small parasitic components compared to bulk CMOS, which improves insertion loss at high frequency and supports wider bandwidth. For a series switch, three configurations are proposed: using the collector as an input (CI), using the emitter as an input (EI), and using a combination of the two in an antiparallel (AP) fashion. While all three configurations exhibit similar performance, the SPDT switch with the EI SiGe HBT exhibits the best insertion loss and isolation achieving dc-to-above 110-GHz bandwidth, 2.5 dB of insertion loss, and 27.3 dB of isolation at 60 GHz. The SPDT switch with AP SiGe HBT pair exhibits the highest linearity, with 15.6 dBm of input 1-dB compression point (IP 1 dB) at 10 GHz. With 0.61 mW of power dissipation, these new SPDT switches using SiGe HBTs exhibit similar performance to silicon-on-insulator (SOI) CMOS while obtaining higher power capability among conventional series-shunt SPDT designs.

A 6-bit active digital step attenuator (DSA), which simultaneously achieves wide bandwidth, flat gain characteristics, and bidirectional operation, is proposed for wideband phased-array antennas. In addition, it supports bandwidth tuning and equalization function to reduce complexity and physical size of systems. The proposed circuit utilizes an active double-pole double-throw switch, which provides positive gain with four-way switching and bidirectional operation. In addition, the simplified switched T-type topologies are applied to improve the insertion loss and save on chip area for low-attenuation states (0.5, 1, and 2 dB). Implemented in a 130-nm SiGe-BiCMOS technology platform, the proposed active DSA provides the advantages of seamless integration with digital control blocks and wide operational bandwidth due to its low parasitic capacitance. The active DSA exhibits flat in-band gain of >7 dB and the input/output return losses <9 dB from 2 to 20 GHz, which covers S-, C-, X-, and Ku-bands. In addition, it shows the root-mean-square amplitude and phase errors of <0.3 dB and <3.4°, respectively. The measured output 1-dB compression point is -3.6 dBm with a dc power consumption of 75 mW. The chip area of the active DSA is 1.43 x 1.23 mm², including pads.

A power divider/combiner circuit, which simultaneously achieves wide bandwidth, flat gain characteristics, and bidirectional operation, is proposed for multichannel broadband system applications. The proposed circuit utilizes cascode-based bidirectional amplifier cores, which steer the operation modes between a divider and a combiner depending on the control input, and a two-stage distributed-amplifier topology with artificial transmission lines. Implemented in a 130-nm silicon–germanium BiCMOS technology platform, the proposed divider/combiner provides the advantage of seamless integration with digital control blocks. The power divider/combiner exhibits the flat in-band gain of 9 dB and the operational bandwidth of 2–22 GHz, which covers $S$ -, $C$ -, $X$ -, and $Ku$ -bands. In addition, it shows the amplitude imbalance of 0.8 dB, the phase imbalance of 3.5°, the port-to-port isolation of 22 dB, the output 1-dB compression point of 3 dBm, and good impedance matching under 100-mW dc power consumption.

Best practice in mitigation strategies for single-event transients (SETs) in radio-frequency (RF) receiver modules is investigated using a variety of integrated receivers utilizing inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). The receivers were designed and implemented in a 130-nm SiGe BiCMOS technology platform. In general, RF switches, low-noise amplifiers (LNAs), and downconversion mixers utilizing inverse-mode SiGe HBTs exhibit less susceptibility to SETs than conventional RF designs, in terms of transient peaks and duration, at the cost of RF performance. Under normal RF operation, the SET-hardened switch is mainly effective in peak reduction, while the LNA and the mixer exhibit reductions in transient peaks as well as transient duration.

This brief presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances ( $\text{C}_{OFF}$ ) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective $\text{C}_{OFF}$ , enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1°.