In this paper, Self-Heating Effect (SHE) of Gate-All-Around (GAA) nanoplate field effect transistor (FET) with variations of active area specifications including number of vertically stacked channels, metal gate thickness, and channel width, is investigated using TCAD simulations. Our research suggests that varying these architecture parameters not only affect overall performance of sub-5-nm node GAA nanoplate FET such as on-current degradation and time-delay, but also greatly impact thermal reliability such as lattice temperature and thermal resistance, which are comprehensively analyzed using the Figure of Merit (FoM). Furthermore, thermal reliability of GAA nanoplate-FET is analyzed from perspective of Hot Carrier Injection (HCI) / Bias Temperature Instability (BTI) lifetime variation using maximum lattice temperature (TL,max) and metal gate thickness (TM).

Basic gate stack structure of the Ferroelectric FET is Metal-ferroelectric-insulator-silicon (MFIS), where the memory window (M.W) is 2*(P _r -Q _it )/C _FE considering the trapped charge. However, in Metal - insulator - ferroelectric - insulator - silicon (MIFIS) gate-stacked FeFETs, the M.W is 2*{(P _r -Q _it )/C _FE + (Q’ _it -Q _it )/C _G.IL )}, which allows the M.W to widen in case the Q’ _it injected from the gate side is larger than the Q _it injected from the channel side. In this paper, we propose a band engineered (BE) gate insulator in MIFIS gate-stacked FeFETs. This lowers the energy barrier of the hole when applying the program voltage, thereby increasing the amount of hole injected from the gate side, and consequently widening the M.W. Furthermore, it is demonstrated by TCAD simulation that the physical origins of Vt shift of PGM state is hole injection. In addition, in the case of BE-MIFIS gate-stacked FeFETs, the maximum ISPP slope is increased by about 2 times compared to conventional MIFIS, which is an important feature in ferroelectric VNAND (FeVNAND) operated at low voltage.

In this paper, self-heating effects (SHEs) in three-stacked nanoplate FETs were investigated through the TCAD simulation. In order to obtain high reliability, the evaluation of SHEs was performed after I _D -V _G curve fitting based on the experimental data. First, general analysis on SHEs was conducted to confirm the influence of SHEs to electrical characteristics. The optimized nanoplate width for great electrical properties was proposed by using the figure-of-merit factor under the consideration of SHEs. In addition, difference of heat flux between FinFET and stacked nanoplate FET was analyzed. Based on the analysis, the two-step thermal resistance (R _th ) model depending on drain voltage was proposed. The two-step R _th model in the stacked nanoplate FET matched well with the Berkeley short-channel IGFET model-common multigate model compared the other R _th models. A seven-stage ring oscillator with the proposed R _th model was demonstrated, and SHEs in the circuit level were confirmed.

In this article, a reliable static random access memory (SRAM) circuit design is proposed for improved thermal and electrical performance at 5-nm technology nodes. The proposed SRAM circuit is developed by incorporating bottom-up approach (from device level to circuit level). The proposed device/circuit design utilizes high thermal conductivity and high permittivity of titanium dioxide (TiO $_{\text{2}}$ ). Specifically, TiO $_{\text{2}}$ -based vertically stacked nanosheet field-effect transistor (NSFET) in the proposed SRAM shows the improvement of maximum lattice temperature ( $\textit{T}_{\text{MAX}}$ ) from 564 to 431 K, which enables the improvement of electron mobility ( $\mu _{\text{electron}}$ ) by 53.1%. In addition, the proposed device structure shows the improvement of ON-current ( $\textit{I}_{\text{on}}$ )/gate current ( $\textit{I}_{\text{gate}}$ ), by 18%/1000%, compared to hafnium oxide (HfO $_{\text{2}}$ )-based vertically stacked NSFET. Because of this thermal/electrical performance boosting, the proposed SRAM circuit shows the enhancement of hold-signal-to-noise margin SNM (HSNM), read-SNM (RSNM), read access time (RAT), and write access time (WAT) at the same time. This thermal and electrical co-improvement indicates that the proposed device structure could enable reliable IC chip design.

In this paper, the structural and material optimization of gate sidewall spacer in the perspective of off-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of off-state leakage current, and active performance (on-current, on/off current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~ 78%, and then on/off current ratio (Ion/Ioff) was enhanced by 4.2 times. On-current (Ion) according to contact resistance (Rcon) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced Ion/Ioff by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.