With the rising importance of energy efficiency, zero leakage power and instant-on capability are highly desired features in energy harvesting sensors, as well as “normally off” high performance processors. However, intermittent power in such systems requires nonvolatile memory (NVM) to hold intermediate data and avoid rollbacks. Previous work has adopted FeRAM and STT-MRAM to achieve zero-standby power and fast-restore nonvolatile processors (NVPs) [1-3]. Previous NVPs, however, suffer from several drawbacks: 1) Various power interrupt periods are not considered; 2) the 2-macro memory architecture slows access speed; 3) worst-case store/restore operations are always performed. We present a 65nm fully-CMOS-logic-compatible ReRAM-based NVP achieving time/space-adaptive data retention. A 1-macro nvSRAM with self-write-termination (SWT) is integrated to boost clock frequency and reduce store energy. The adaptive retention and SWT strategy relieve the ReRAM write endurance challenge (106-1012), making it sufficient for most applications. The NVP operates at 100MHz with 20ns/0.45nJ restore time (TRESTORE)/energy (ERESTORE), realizing 6× reduction in TRESTORE, >6000× reduction in ERESTORE and 4× higher clock frequency compared with existing designs.

Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau–Lifshitz–Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%–87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.

Domain-wall memory (DWM) has SRAM class access performance, low energy, high endurance, high density, and CMOS compatibility. Recently, shift reliability and processing-using-memory (PuM) proposals developed a need to count the number of parallel or anti-parallel domains in a portion of the DWM nanowire. In this paper we propose a multi-domain magneto-tunnel junction (MTJ) that can detect different resistance levels as a function of a the number of parallel or anti-parallel domains. Using detailed micromagnetic simulation with LLG, we demonstrate the multi-domain MTJ, study the benefit of its macro-size on resilience to process variation and present a macro-model for scaling the size of the multi-domain MTJ. Our results indicate scalability to seven-domains while maintaining a 16.3mV sense margin.

Resistance-based memory devices are considered as a strong candidate for next-generation nonvolatile memories as well as potential application in high density embedded cache. These devices can be programmed to different resistance states by applying electrical bias. Read operation then senses the programmed state by discharging a shared data line through the memory cell. However, as the dimensions of the device scale down, its resistance increases and the distribution widens, which leads to reduced sensing margins and degradation in read performance. In the proposed dual-data line (DDL) read scheme, we recycle current flowing through the memory cell during the read operation to create an additional voltage swing on a secondary data line, and combine it with the signal on the original data line to reduce sensing time and energy. Performance comparison with the conventional read scheme is derived theoretically by using circuit analysis and verified through simulation on an array critical path constructed in 65-nm technology. Results show that the DDL scheme can improve sensing margins by an average of 86%, which translates to a sensing time reduction of 47%, across various device conditions. For the same read performance, the sensing energy is decreased by 48%.

The extreme complexity of the brain has attracted the attention of neuroscientists and other researchers for a long time. More recently, the neuromorphic hardware has matured to provide a tool to study neuronal dynamics. Here, we study neuronal dynamics using different sets of settings on a neuromorphic chip built with flexible parameters of neuron models. Our unique setting in the network of leaky integrate-and-fire (LIF) neurons is to introduce a weak noise environment. We observed three different types of collective neuronal activities, each with a clear boundary separating the different types of activity (phase transition). From this, we constructed a brain phase diagram and discovered that a noise-induced phase (N-phase), which is dominated by neuronal avalanche activity (intermittent aperiodic neuron firing), emerges in the presence of noise. The dynamics can be manipulated in this N-phase. The discovery of the noise-induced phase is consistent with the literature that analysis of the natural brain ...