Federated learning is a distributed machine learning method for learning consumer data generated by consumer electronic devices. It provides personalized intelligent services for users while maintaining data privacy by sharing models instead of user data. It is challenging for these methods to learn data efficiently and with high quality. The performance and quality of the model in federated learning are affected by differences in data from different devices, which can lead to divergence between local and global models. Therefore, this paper proposes a parameter importance-based optimization federated learning method, FedPIA. First, two key indicators, including the rate of parameter change and the acceleration rate of parameter change, are provided to evaluate the importance of model parameters, which can reflect the divergence of the data from different devices. Then, a regular term is created based on these indicators to construct a new loss function, reducing the divergence between local and global models. Last, this paper efficiently trains a high-quality model on consumer data with this optimization approach. Experiments show that FedPIA is significantly better than FedCL, FedAvg, and Scaffold in accuracy, F1 scores and communication overhead.

Equi-join operations are fundamental in database management. Hash join algorithms are often used to reduce the computational complexity of join operations; however, their performance is influenced by imperfect data distributions caused by hash collisions. To resolve these collisions, this study designs a hardware-accelerated hash join architecture. This architecture aims to break the trade-off between complex hash functions, which is computationally expensive, and hash join performance. First, two hash functions are employed to distribute data as evenly as possible, and then multiple entries of the collision list are provided; finally, a small number of the static random-access memory (SRAM) of the field-programmable gate arrays (FPGAs) are used to conduct the join operation in parallel. The proposed method yields high-throughput and is resource-efficient, as it does not require reprocessing of data; further, it improves hash table utilization. The results of implementing this architecture on a Xilinx Zynq FPGA platform indicate an accelerated throughput that is a minimum of 4.2× that of previous hardware-accelerated hash join methods.

Federated Learning (FL) empowers multiple clients to collaboratively learn a global generalization model without the need to share their local data, thus reducing privacy risks and expanding the scope of AI applications. However, current works focus less on data in a highly nonidentically distributed manner such as graph data which are common in reality, and ignore the problem of model personalization between clients for graph data training in federated learning. In this paper, we propose a novel personality graph federated learning framework based on variational graph autoencoders that incorporates model contrastive learning and local fine-tuning to achieve personalized federated training on graph data for each client, which is called FedVGAE. Then we introduce an encoder-sharing strategy to the proposed framework that shares the parameters of the encoder layer to further improve personality performance. The node classification and link prediction experiments demonstrate that our method achieves better performance than other federated learning methods on most graph datasets in the non-iid setting. Finally, we conduct ablation experiments, the result demonstrates the effectiveness of our proposed method.

Join is a data-intensive and compute-intensive operation in database systems. As most existing solutions to accelerate the hash join operation on field programmable gate array (FPGA) are focused on N-to-1 join relationships, their performances rapidly decline on N-to-M joins. To resolve this shortcoming, this study proposes a novel architecture combining hash and sort-merge algorithms for join acceleration. In the build phase, the architecture utilizes a single hash function to build hash tables for two data tables, and the hash collisions are addressed by building ordered linked lists according to their join attributes. In the merge phase, mapped buckets in two hash tables are merged one-to-one to find matching tuples. This architecture lends itself to high parallelism to improve its performance. Experimental results show that the design on a FPGA achieved a high join throughput of 194.0 million tuples per second, which is better than the reported FPGA implementations. Moreover, the architecture is perfectly compatible with both N-to-1 and N-to-M join relationships.

As semiconductor technology evolves, computing platforms attempt to integrate hundreds of processing cores and associated interconnects into a single chip. Network-on-chip (NoC) technology has been widely used for data exchange centers in recent years. As the core element of the NoC, the round-robin arbiter provides fair and fast arbitration, which is essential to ensure the high performance of each module on the chip. In this paper, we propose a low-latency fair switch arbiter (FSA) architecture based on the tree structure search algorithm. The FSA uses a feedback-based parallel priority update mechanism to complete the arbitration within the leaf nodes and a lock-based round-robin search algorithm to guarantee global fairness. To reduce latency, the FSA keeps the lock structure only at the leaf node so that the complexity of the critical path does not increase. Meanwhile, the FSA achieves a critical path with only $O\left(lo{g}_{4}N\right)$ delay by using four input nodes in parallel. The latency of the proposed circuit is on average 22.2% better than the existing fair structures and 8.1% better than the fastest arbiter, according to the synthesis results. The proposed architecture is well suited for high-speed network-on-chip switches and has better scalability for switches with large numbers of ports.

The hash join operator is one of the most important relational operations used in database. The offloading and acceleration of this operation on hardware has been a technique of growing interest for a long time. However, the non-uniform distribution of data caused by hash collisions negatively affects the throughput of the hash join algorithm, owing the variation in the number of hash table accesses required for each lookup. To resolve this issue, a non-collision parallel static random-access memory (SRAM)-based hash join architecture is presented. This architecture utilizes multiple hash functions and content addressable memories (CAMs) to eliminate hash collision, thereby ensuring a worst constant memory access for each phase in the hash join algorithm and consequently improving the hash join throughput. The proposed architecture was implemented on a Xilinx field programmable gate array (FPGA), and the experimental results show that our design achieved a high hash join throughput of 153.6 million tuples per second, and a speedup factor of at least 2.5 with the best existing FPGA-based hash join architecture and a match rate of 50%.