As a valuable topic in wireless communication systems, automatic modulation classification has been studied for many years. In recent years, recurrent neural networks (RNNs), such as long short-term memory (LSTM), have been used in this area and have achieved good results. However, these models often suffer from the vanishing gradient problem when the temporal depth and spatial depth increases, which diminishes the ability to latch long-term memories. In this paper, we propose a new hierarchical RNN architecture with grouped auxiliary memory to better capture long-term dependencies. The proposed model is compared with LSTM and gated recurrent unit (GRU) on the RadioML 2016.10a dataset, which is widely used as a benchmark in modulation classification. The results show that the proposed network yields a higher average classification accuracy under varying signal-to-noise ratio (SNR) conditions ranging from 0 dB to 20 dB, even with much fewer parameters. The performance superiority is also confirmed using a dataset with variable lengths of signals.

This brief presents a new algorithm optimized for radix-2 real-valued fast Fourier transform (RFFT) through rigorous formula derivation. Based on that, a novel two-parallel pipelined radix-2 RFFT architecture is proposed with only real datapaths instead of hybrid datapaths. The architecture takes advantage of saving arithmetic resource in the time-division multiplexing approach to achieve 100% hardware resource utilization. Thereby it reduces the required number of complex multipliers from log2N

Equi-join operations are fundamental in database management. Hash join algorithms are often used to reduce the computational complexity of join operations; however, their performance is influenced by imperfect data distributions caused by hash collisions. To resolve these collisions, this study designs a hardware-accelerated hash join architecture. This architecture aims to break the trade-off between complex hash functions, which is computationally expensive, and hash join performance. First, two hash functions are employed to distribute data as evenly as possible, and then multiple entries of the collision list are provided; finally, a small number of the static random-access memory (SRAM) of the field-programmable gate arrays (FPGAs) are used to conduct the join operation in parallel. The proposed method yields high-throughput and is resource-efficient, as it does not require reprocessing of data; further, it improves hash table utilization. The results of implementing this architecture on a Xilinx Zynq FPGA platform indicate an accelerated throughput that is a minimum of 4.2× that of previous hardware-accelerated hash join methods.

This paper presents a low-latency coordinate rotation digital computer (CORDIC) algorithm to accelerate the computation of arctangent functions, and it describes the corresponding iterative and pipelined architecture of this novel algorithm. As compared to the existing methods based on CORDIC, the proposed method can effectively reduce the number of iterations by dedicated pre-rotation and comparison processes. Moreover, the proposed CORDIC algorithm supports all vectors with arbitrary angles while maintaining convergence. By error analysis, the proposed algorithm can achieve the same accuracy as the conventional CORDIC algorithm during floating-point arctangent function computation and reduce the number of iterations by approximately 50%. This paper presents two new architectures—the iterative architecture, which can be more resource efficient, and the pipelined architecture, which can achieve a throughput rate of one datum per clock. Finally, the experimental comparison results indicate that the proposed method outperforms extant methods as it exhibits low latency, requires fewer resources to compute the arctangent function for floating-point inputs, and necessitates no digital signal processing (DSP) and memory for fixed-point inputs.

The offloading and acceleration of database operations on field programmable gate arrays (FPGAs) have been extensively studied for a long time. Architectures of join, a key database operation, have been proposed and optimized on FPGAs. However, these join architectures are either resource-intensive or have low-throughput. In this paper, we focus on the equi-join and propose a resource-efficient join architecture based on a tree model. The architecture needs two phases: the build phase, in which a binary tree is built by using the first database table, and the probe phase, in which the architecture searches the tree to find matching solutions through a second database table. In addition, we propose a parallel implementation for this architecture to improve its performance. The proposed design was implemented on a Xilinx FPGA, and the results were compared with the most recent works on hardware join. The experimental results demonstrate that for a range of parallelism and dataset sizes, our design achieves a data throughput of 8–100 million tuples per second, which is compatible with the bus rate, and performs well in balancing resource utilization and data throughput.

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for $N$ -point RFFT with $W$ -bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.