Switches play a critical role as core components in data center networks. The advent of multi-die chiplet packaging as a prevailing trend in complex chip development presents challenges in designing the multi-die packaging of switch chips. With limited inter-die connections in mind, we propose a scalable, unified switch architecture optimized for efficient connectivity. This architecture includes the strategic mapping of data queues, meticulous planning of data paths, and the integration of a unified interface, all aiming to facilitate efficient switch operations within constrained connectivity environments. Our optimization efforts encompass various areas, including refining arbitration strategies, managing mixed unicast and multicast transmissions, and mitigating network congestion to alleviate bottlenecks in data flow. These enhancements contribute to heightened levels of performance and robustness in the switching process. During the validation phase, the structure we propose reduced interconnection usage between dies by 25%, while supporting functions such as unicast and multicast transmissions.

As semiconductor technology evolves, computing platforms attempt to integrate hundreds of processing cores and associated interconnects into a single chip. Network-on-chip (NoC) technology has been widely used for data exchange centers in recent years. As the core element of the NoC, the round-robin arbiter provides fair and fast arbitration, which is essential to ensure the high performance of each module on the chip. In this paper, we propose a low-latency fair switch arbiter (FSA) architecture based on the tree structure search algorithm. The FSA uses a feedback-based parallel priority update mechanism to complete the arbitration within the leaf nodes and a lock-based round-robin search algorithm to guarantee global fairness. To reduce latency, the FSA keeps the lock structure only at the leaf node so that the complexity of the critical path does not increase. Meanwhile, the FSA achieves a critical path with only $O\left(lo{g}_{4}N\right)$ delay by using four input nodes in parallel. The latency of the proposed circuit is on average 22.2% better than the existing fair structures and 8.1% better than the fastest arbiter, according to the synthesis results. The proposed architecture is well suited for high-speed network-on-chip switches and has better scalability for switches with large numbers of ports.

The hardware-based computation of arcsine and arccosine functions is predominantly realized through the vectoring-mode CORDIC algorithm. However, existing approaches necessitate computationally intensive calculations or suffer from approximation-induced errors. This brief proposes a hybrid architecture that replaces the sequentially dependent early iterations with an efficient table-based mapping. By reinterpreting the initial convergence process as a non-uniform domain segmentation problem, the proposed Prefix Binary Tree Mapping (PBTM) achieves algorithmic look-ahead through direct indexing of precomputed intermediate states, thereby bypassing the coarse-grained decision stages. Experimental results demonstrate that by substituting the early iterations with precise state mapping, the PBTM-CORDIC method suppresses approximate gain error below the quantization noise floor and reduces the worst-case error by 76.02%. Furthermore, hardware implementation confirms a 22.77% reduction in area and a 56.08% enhancement in energy efficiency compared to state-of-the-art pipelined designs.

Join is an important but data-intensive and compute-intensive operation in database systems. Moreover, there are multiple types of join operations according to different join conditions and data relationships with diverse complexities. Because most existing solutions for accelerating the join operation on field programmable gate arrays (FPGAs) focus only on the easiest join application, this study presents a novel architecture that is suitable for multiple types of join operation. This architecture has a modular design and consists of three components that are executed sequentially and in pipeline. Specifically, the top-K sorter is used instead of the full sorter to reduce resource utilization and advance the merge processing. Further, the architecture is perfectly compatible with both N-to-1 and N-to-M join relationships, and can also adapt well to both equi-join and band-join. Experimental results show that this design, which is implemented on an FPGA, achieved a high join throughput of 242.1 million tuples per second, which is better than other reported FPGA implementations.